Date:   Tue, 14 Mar 2023 12:42:22 +0100
From:   Piotr Raczynski <piotr.raczynski@intel.com>
To:     Serge Semin <Sergey.Semin@baikalelectronics.ru>
CC:     Giuseppe Cavallaro <peppe.cavallaro@st.com>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Jose Abreu <joabreu@synopsys.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        "Jakub Kicinski" <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        "Andrew Lunn" <andrew@lunn.ch>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Serge Semin <fancer.lancer@gmail.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
        Christian Marangi <ansuelsmth@gmail.com>,
        Biao Huang <biao.huang@mediatek.com>,
        Yang Yingliang <yangyingliang@huawei.com>,
        <netdev@vger.kernel.org>,
        <linux-stm32@st-md-mailman.stormreply.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net 05/13] net: stmmac: Enable ATDS for chain-mode
Message-ID: <ZBBdnu2OkCRFRinT@nimitz>
References: <20230313224237.28757-1-Sergey.Semin@baikalelectronics.ru>
 <20230313224237.28757-6-Sergey.Semin@baikalelectronics.ru>
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20230313224237.28757-6-Sergey.Semin@baikalelectronics.ru>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?zF3X7iuDdnNcL/Mimz68Dps5HZSA32jAKSeDg4Z2OxhgQBsEDsjPEwQhpvbL?=
 =?us-ascii?Q?+b76kIqOIHv+WMB5zVZz3qvpM6vsGzlQ/tcYFWcrwQIOPyK6V5DZlYEcANp1?=
 =?us-ascii?Q?soskwkcv/PWTMCt7tlTkt84f9dgZWmGovvOENZnFCoeGrjMJm8/Ew5exR+Ab?=
 =?us-ascii?Q?dIMvq+Kjk206miVx9GtLjxnaOwrQsZI1u0TAANuG9rCUJi3w6tcgZG3E7m1Y?=
 =?us-ascii?Q?J4rUGiMrm08/M5kqeS6NgpGIXj6xwkWGEjSh+F75zDWbVYfa17nVHWfsTalC?=
 =?us-ascii?Q?SAXcaf3+39rwP4Y8JqkNd46ZBgpewN01l0BEA7pE8/506mvtFxhilW+a9fN6?=
 =?us-ascii?Q?gVmwdBb4bhsNlpBxYbgBDzM3+mMlFDGeza81aVxTttX3QSLZIZ8VbDanLp/m?=
 =?us-ascii?Q?HesfH5b9c1LxqtXA7SUa3UDAmD7tFoIacSzyTvnBN8ktoHXayO/6aijg4vAd?=
 =?us-ascii?Q?/PLowJ7NDBzmyyTZWMMxFlmEI8a3hXygSEGJNh+LrWuTOGJ87nRWqMgmrTbq?=
 =?us-ascii?Q?oYtASo4GL6skYzJsevYDtCyGjj5sIR+zvn/Cmgaur3oSNi6ytIN+RxGCR+a9?=
 =?us-ascii?Q?WFZan3xncBqZKe79hJAmZrfsor2Ub8UlILiMtu2pjYjsUyx856RVfjjzR0BJ?=
 =?us-ascii?Q?ZaNQXzMVoaajoEZVf6aSldGRVv8JOt/v29mDjCwP8v194Vgv+x98lzh/3DnM?=
 =?us-ascii?Q?7nO2m75KSyv46PzTjIGdyX8uHgXmyQnzjV2QMl6XoAGDLYuJmo6RDLpAEur3?=
 =?us-ascii?Q?KDkfSk0Zj2O5Ss3Nb2Gcl2CQ64CN17nBYFykpjF+CjYHGtL4UNI0dRhwM3AT?=
 =?us-ascii?Q?/gHYvKHkTPyhr/5jM9A3Nc1QZnVvvjxh4mtydXRxwKAnJ0+8rMV0dgmiTK/C?=
 =?us-ascii?Q?cXYgJfmcrdNnqP3iZCCojE1Imy9GtEz6mMe6TAXW+P3OYzHk/Jds1bQPddY3?=
 =?us-ascii?Q?+aOmbZ057ldOTt5V2mmivAqJjfPVQdowJkRdqwSHbbOIFFXfbxv6TjDn0UPZ?=
 =?us-ascii?Q?/nOhuOHLC51UeqmDf/V7V+d9EuBQjRl16hBotaN7w9Paq/H60v12gw7TH0ll?=
 =?us-ascii?Q?t+obh8VvgiCvz+LRNa2PPiS9u4CsuttPDQYI5aLrEQYX42aCrqAt9VsWYBZ8?=
 =?us-ascii?Q?Sz3vCkM8aD9TeZmWOEUXYaVF0tOU7mvJZ+N+bTAAySCuMkLPK41KiDKossoy?=
 =?us-ascii?Q?gABRf5P79ZkyYt5xp6m95P53hJ9zCgHhEWzr8QNEa6F//UbTjVS7UWWMPM+P?=
 =?us-ascii?Q?I2KPo9oMgy4CWjBuvNYV3H+QMMlcRmPI1DPB9jkxAUEl97z+vENxyV7NE1ZE?=
 =?us-ascii?Q?SGYYDPy4qI1WT4pEMIqZQ3vLW1scdlCWyDVyf4g2vUrl9phaiLlmEmePXICF?=
 =?us-ascii?Q?tSUObSOoILMXe9v74hRMxf1ecqmrVR8H2OnCJzZcoEXQeC01sxYooLx9WOFg?=
 =?us-ascii?Q?hv+fKXCjImGk3KvBYY9MD23cFmoco13PCpbz+SE/0iEXiUDgUSn3TvpH0SPK?=
 =?us-ascii?Q?7oxqQTsL5bcjoO/GRqxZAHIgK8Rke/kwipbS3e9oEZGFXTGmCM5N53vxcEo2?=
 =?us-ascii?Q?oGPTeEqRJF4VDIey2NEwUg8E61bti8FhlVhCt04bcGz23dWsgLjEe7nq//4v?=
 =?us-ascii?Q?og=3D=3D?=
X-MS-Exchange-CrossTenant-Network-Message-Id: 1c0a9da1-f780-4e60-e2b1-08db248131c6
X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB7471.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2023 11:42:30.9599
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: feDt62s/UthHqYMzUxDDa5V1m2TJlKBrevOaMUP/tK/F4D0wI8DedeL5zgXlq9P/13Cs4fI+jvbQcr0d2IekVekmCTk3xyR0pqIpb+MjE3Y=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5646
X-OriginatorOrg: intel.com
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Tue, Mar 14, 2023 at 01:42:29AM +0300, Serge Semin wrote:
> It wasn't stated why the Alternate Descriptor Size shouldn't have been
> changed for the chained DMA descriptors, while the original commit did
> introduce some chain_mode.c modifications. So the ATDS-related change in
> commit c24602ef8664 ("stmmac: support extend descriptors") seems
> contradicting. Anyway from the DW MAC/GMAC hardware point of view there is
> no such limitation - whether the chained descriptors can't be used
> together with the extended alternate descriptors. Moreover not setting the
> BUS_MODE.ATDS flag will cause the driver malfunction in the framework of
> the IPC Full Checksum and Advanced Timestamp feature, since the later
> features require the additional 4-7 dwords of the DMA descriptor to set
> some flags and a timestamp. So to speak in order to have all these
> features working correctly in the chained mode too let's make sure the
> ATDS flag is set irrespectively from the DMA descriptors mode.
> 
> Fixes: c24602ef8664 ("stmmac: support extend descriptors")
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> ---
>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 2ed63acaee5b..ee4297a25521 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -2907,7 +2907,6 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)
>  	struct stmmac_rx_queue *rx_q;
>  	struct stmmac_tx_queue *tx_q;
>  	u32 chan = 0;
> -	int atds = 0;
>  	int ret = 0;
>  
>  	if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
> @@ -2915,9 +2914,6 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)
>  		return -EINVAL;
>  	}
>  
> -	if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
> -		atds = 1;
> -
>  	ret = stmmac_reset(priv, priv->ioaddr);
>  	if (ret) {
>  		dev_err(priv->device, "Failed to reset the dma\n");
> @@ -2925,7 +2921,8 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)
>  	}
>  
>  	/* DMA Configuration */
> -	stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
> +	stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg,
> +			priv->extend_desc);
>  
>  	if (priv->plat->axi)
>  		stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
> -- 
> 2.39.2
> 
> 
Looks fine, thanks.
Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com>