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References: <20230314124404.117592-1-xingyu.wu@starfivetech.com>
Subject: Re: [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        Xingyu Wu <xingyu.wu@starfivetech.com>,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
To:     Emil Renner Berthing <kernel@esmil.dk>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Xingyu Wu <xingyu.wu@starfivetech.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Date:   Tue, 14 Mar 2023 17:30:17 -0700
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Quoting Xingyu Wu (2023-03-14 05:43:53)
> This patch serises are to add new partial clock drivers and reset
> supports about System-Top-Group(STG), Image-Signal-Process(ISP)
> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC.

What is your merge plan for this series? Did you intend for clk tree to
take the majority of patches? We won't take the dts changes through the
clk tree.

I think Philipp Zabel reviewed some earlier version of the patches and
provided reviewed-by tags. Can you check if they can be added here? If
so, please resend again, or get those merged through the reset tree.