Message-ID: <32f57c8a-61a4-13ec-a4ce-e1f5d45e45d7@ti.com>
Date:   Wed, 15 Mar 2023 09:32:57 +0530
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        <robh+dt@kernel.org>, <krzysztof.kozlowski@linaro.org>,
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        <s-vadapalli@ti.com>
Subject: Re: [PATCH 2/2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
To:     Andrew Davis <afd@ti.com>
References: <20230314104055.1475054-1-s-vadapalli@ti.com>
 <20230314104055.1475054-3-s-vadapalli@ti.com>
 <88e8617c-7b88-238d-2097-bfc25c0f9bf7@ti.com>
Content-Language: en-US
From:   Siddharth Vadapalli <s-vadapalli@ti.com>
In-Reply-To: <88e8617c-7b88-238d-2097-bfc25c0f9bf7@ti.com>
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Hello Andrew,

On 15/03/23 03:40, Andrew Davis wrote:
> On 3/14/23 5:40 AM, Siddharth Vadapalli wrote:
>> Add device tree support to enable MCU CPSW with J784S4 EVM.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 ++++++++++++++++++++++++
>>   1 file changed, 47 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> index 8cd4a7ecc121..05db64ed0706 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> @@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35)
>> MCAN15_RX.GPIO0_8 */
>>       };
>>   };
>>   +&wkup_pmx0 {
>> +    mcu_cpsw_pins_default: mcu-cpsw-pins-default {
>> +        pinctrl-single,pins = <
>> +            J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
>> +            J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
>> +            J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
>> +            J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
>> +            J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
>> +            J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
>> +            J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
>> +            J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
>> +            J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
>> +            J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
>> +            J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
>> +            J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38)
>> MCU_RGMII1_TX_CTL */
>> +        >;
>> +    };
>> +
>> +    mcu_mdio_pins_default: mcu-mdio-pins-default {
>> +        pinctrl-single,pins = <
>> +            J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
>> +            J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
>> +        >;
>> +    };
>> +};
>> +
>>   &main_uart8 {
>>       status = "okay";
>>       pinctrl-names = "default";
>> @@ -194,3 +220,24 @@ &main_sdhci1 {
>>   &main_gpio0 {
>>       status = "okay";
>>   };
>> +
>> +&mcu_cpsw {
>> +    status = "okay";
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
> 
> Move the mcu_mdio_pins_default pinctrl to the mdio node below.

Thank you for reviewing the patch. I will fix it and post the v2 patch.

Regards,
Siddharth.