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From:   Huacai Chen <chenhuacai@kernel.org>
Date:   Wed, 15 Mar 2023 14:24:32 +0800
Message-ID: <CAAhV-H6j1iCujsXFRCic0LS=cwkwSDz+8_YMWz9ZO+tZ4y3K3w@mail.gmail.com>
Subject: Re: [PATCH V2] LoongArch: Make WriteCombine configurable for ioremap()
To:     Xi Ruoyao <xry111@xry111.site>
Cc:     Huacai Chen <chenhuacai@loongson.cn>, loongarch@lists.linux.dev,
        Xuefeng Li <lixuefeng@loongson.cn>,
        Guo Ren <guoren@kernel.org>, Xuerui Wang <kernel@xen0n.name>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn
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On Wed, Mar 15, 2023 at 12:33=E2=80=AFPM Xi Ruoyao <xry111@xry111.site> wro=
te:
>
> On Wed, 2023-03-15 at 08:44 +0800, Huacai Chen wrote:
>
> /* snip */
>
> > +config ARCH_WRITECOMBINE
> > +       bool "Enable WriteCombine (WUC) for ioremap()"
> > +       help
> > +         LoongArch maintains cache coherency in hardware, but when pai=
red
> > +         with LS7A chipsets the WUC attribute (Weak-ordered UnCached, =
which
> > +         is similar to WriteCombine) is out of the scope of cache cohe=
rency
> > +         machanism for PCIe devices (this is a PCIe protocol violation=
, which
> > +         may be fixed in newer chipsets).
> > +
> > +         This means WUC can only used for write-only memory regions no=
w, so
> > +         this option is disabled by default, making WUC silently fallb=
ack to
> > +         SUC for ioremap(). You can enable this option if the kernel i=
s ensured
> > +         to run on hardware without this bug.
>
> 'You can override this setting via writecombine=3Dyes/no boot parameter.'
OK, thanks.

>
> /* snip */
>
> > +static int __init setup_writecombine(char *p)
> > +{
> > +       if (!strcmp(p, "on"))
> > +               pgprot_wc =3D PAGE_KERNEL_WUC;
> > +       else if (!strcmp(p, "off"))
> > +               pgprot_wc =3D PAGE_KERNEL_SUC;
>
> else
>         pr_warn("Unknown writecombine setting \"%s\".\n", p);
OK, thanks.

Huacai
>
> Otherwise LGTM.
>
> --
> Xi Ruoyao <xry111@xry111.site>
> School of Aerospace Science and Technology, Xidian University