Date:   Wed, 15 Mar 2023 08:14:06 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Xingyu Wu <xingyu.wu@starfivetech.com>,
        Stephen Boyd <sboyd@kernel.org>
Cc:     Stephen Boyd <sboyd@kernel.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        Rob Herring <robh+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 00/11] Add new partial clock and reset drivers for
 StarFive JH7110
Message-ID: <e895fea6-e13b-450f-97e8-34ecfe075691@spud>
References: <20230314124404.117592-1-xingyu.wu@starfivetech.com>
 <de14f63beb2b3e424ec2375187c8087f.sboyd@kernel.org>
 <729b1b69-aba6-4623-cf78-b08562d30d76@starfivetech.com>
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Hey Stephen,

On Wed, Mar 15, 2023 at 11:44:00AM +0800, Xingyu Wu wrote:
> On 2023/3/15 8:30, Stephen Boyd wrote:
> > Quoting Xingyu Wu (2023-03-14 05:43:53)
> >> This patch serises are to add new partial clock drivers and reset
> >> supports about System-Top-Group(STG), Image-Signal-Process(ISP)
> >> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC.
> >=20
> > What is your merge plan for this series? Did you intend for clk tree to
> > take the majority of patches? We won't take the dts changes through the
> > clk tree.

FWIW, I've been waiting for the "main" clock/reset series [1] to be ready
to go, before suggesting that I take it (the main series) via the soc
tree. This one is kinda in the same boat, with defines in the dt-binding
headers that are used by both drivers and dts, so splitting the two
doesn't make all that much sense.

As Xingyu points out below, this series depends on the main one, so if I
was to take that via soc, this one would need to go on top, or be
delayed.
At what point does that become too much to go via soc and some sort of
shared tag become needed?

Thanks,
Conor.

> >=20
> > I think Philipp Zabel reviewed some earlier version of the patches and
> > provided reviewed-by tags. Can you check if they can be added here? If
> > so, please resend again, or get those merged through the reset tree.
>=20
> These patches add new clock & reset providers based on the basic clock & =
reset
> of the minimal system which Hal.feng had submitted[1], which are used in =
USB, DMA,
> VIN and Display modules that are merging.
[1]: https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivete=
ch.com/
>=20
> Oh I checked and had not received any comments from Philipp Zabel in earl=
ier version
> of these patches. Maybe it was confused with the patches of the minimal s=
ystem.
>=20
> Best regards,
> Xingyu Wu

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