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References: <20230314221609.22433-1-asmaa@nvidia.com> <20230314221609.22433-2-asmaa@nvidia.com>
In-Reply-To: <20230314221609.22433-2-asmaa@nvidia.com>
From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Wed, 15 Mar 2023 11:15:38 +0200
Message-ID: <CAHp75Vd5NhPcgUokJ0i8ftqVXjSB10q4VfxH9A7wcYhei-s2wA@mail.gmail.com>
Subject: Re: [PATCH v5 1/2] gpio: gpio-mlxbf3: Add gpio driver support
To:     Asmaa Mnebhi <asmaa@nvidia.com>
Cc:     linus.walleij@linaro.org, bgolaszewski@baylibre.com,
        linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-acpi@vger.kernel.org
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On Wed, Mar 15, 2023 at 12:16=E2=80=AFAM Asmaa Mnebhi <asmaa@nvidia.com> wr=
ote:
>
> Add support for the BlueField-3 SoC GPIO driver.
> This driver configures and handles GPIO interrupts. It also enables a use=
r
> to manipulate certain GPIO pins via libgpiod tools or other kernel driver=
s.
> The usables pins are defined via the "gpio-reserved-ranges" property.

Thank you for the update, my comments below.

...

> +         This controller should be used in parallel with pinctrl-mlxbf t=
o
> +         control the desired gpios.

GPIOs

Btw, have you considered renaming that driver to pinctrl-mlxbf3?

...

> +#include <linux/resource.h>

I dunno why you added this one.

The missing ones are:
err.h
io.h

...

> +       raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
> +       gpiochip_enable_irq(gc, offset);

No need to call this under the spin lock, or must be explained why.

> +       writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCA=
USE);
> +
> +       val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       val |=3D BIT(offset);
> +       writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);

...

> +       raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
> +       val =3D readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       val &=3D ~BIT(offset);
> +       writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       gpiochip_disable_irq(gc, offset);

Ditto.

> +       raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
> +}

...

> +/* This function needs to be defined for handle_edge_irq */

handle_edge_irq()

...

> +static const struct acpi_device_id __maybe_unused mlxbf3_gpio_acpi_match=
[] =3D {

Why __maybe_unused?

> +       { "MLNXBF33", 0 },
> +       {}
> +};

--=20
With Best Regards,
Andy Shevchenko