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From:   Bjorn Andersson <andersson@kernel.org>
To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        linux-arm-msm@vger.kernel.org,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Andy Gross <agross@kernel.org>
Subject: Re: [PATCH] arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address
Date:   Wed, 15 Mar 2023 16:35:07 -0700
Message-Id: <167892332561.4030021.8220167893365746546.b4-ty@kernel.org>
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On Thu, 2 Mar 2023 16:47:24 +0100, Krzysztof Kozlowski wrote:
> The second LPASS pin controller IO address is supposed to be the MCC
> range which contains the slew rate registers.  The Linux driver then
> accesses slew rate register with hard-coded offset (0xa000).  However
> the DTS contained the address of slew rate register as the second IO
> address, thus any reads were effectively pass the memory space and lead
> to "Internal error: synchronous external aborts" when applying pin
> configuration.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address
      commit: a5982b3971007161b423b39aa843bdb6713a9d44

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>