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Wed, 15 Mar 2023 17:13:27 -0700 Date: Wed, 15 Mar 2023 17:13:25 -0700 From: Nicolin Chen To: Robin Murphy CC: , , , , , , , , , , Subject: Re: [PATCH v1 04/14] iommu/arm-smmu-v3: Add arm_smmu_hw_info Message-ID: References: <494e36cbb77d49e11427b308868dbc1b0e19fe18.1678348754.git.nicolinc@nvidia.com> <5cc56149-965a-bb47-f23f-6aa9d0ecce4e@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <5cc56149-965a-bb47-f23f-6aa9d0ecce4e@arm.com> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT049:EE_|CH0PR12MB5267:EE_ X-MS-Office365-Filtering-Correlation-Id: 22f5e4d4-c465-4754-00f4-08db25b34589 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ioxHrwDWCXRTnbEme/pnf6LE6VILYxc5/srq7XvB2TPZ/A7NuTYNaifs/1FpXch9zO/7UfEP8CxWYhRmogcqbnZ6FJBbmrq/cj413psh+kKlms4iROTrvMpIQWB8JuByoKgwytFyAPHU1NUKUu1iLTQ/JC+Np8JCHcGVqAi+BlmN0pCl6MypIJNzTQa3rHDPizm30Lr+bz6HiUJAntdok+JJkias9aS1upCCitqyIdfYJjnYLz7kCtZU4tjzoW2w9rivaFIftISSijuuK16ZKQi9o+xeG2IEdMkrblGWRQBznGY4YYBKrJ+ztzH3OAkLeU2cw4EEv4crjeVeXK4CoaYjPxpwVXoR3UQQzaYHYn2Mcl/QbwTHFbiTsxVWlApEctSCFZCG0wMhD5Dka6geS+XDYcFeDkAxVnjpBe+2yRHaY8DpjN5bjSGwNnfhlR+hMe63NbKgkqU5SdN/4HuvoSHM9EL/51BW3VflmNvD7NJ4uQlkuawrN1rSXlgiM96mCz85dsB8N8grzib8Lfh79vgGTqTKMxh4hLJGHMV9NJ2j5SAUTA7u5YuOVx31+GfSQeWMZ+seNzwGpZVPdCCSifkj7cPx32Pd2EAASthDfnPjdJK8ciDTeXETwyp0tQN/UWUoLMB67f3L50BfJV92z/PSH53uwy0v7f09k0Rm0ONCWEmB3UtmqBzNPpshiZgUhTHD1q75OpEshgbue5HiyGvJ35AcqhOWLfwnmNkcLGgfQ+qsf6ZAFjqbt1XmyPEgKrFeWUQzPfFJrcAPrzU+mLwgJ9fNFSNPuLOAhzFbWQx4nEprVoQFkdb+cF8ILKZVxq6hz0VuywITDiOGT3vRcw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(136003)(39860400002)(396003)(376002)(451199018)(40470700004)(46966006)(36840700001)(7636003)(2906002)(41300700001)(83380400001)(7416002)(5660300002)(40460700003)(54906003)(8676002)(40480700001)(55016003)(8936002)(4326008)(6916009)(356005)(70206006)(70586007)(36860700001)(82740400003)(86362001)(316002)(82310400005)(426003)(186003)(478600001)(47076005)(33716001)(336012)(966005)(53546011)(9686003)(26005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2023 00:13:29.7474 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22f5e4d4-c465-4754-00f4-08db25b34589 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5267 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 10, 2023 at 03:28:56PM +0000, Robin Murphy wrote: > External email: Use caution opening links or attachments > > > On 2023-03-10 01:17, Nicolin Chen wrote: > > Hi Robin, > > > > Thanks for the inputs. > > > > On Thu, Mar 09, 2023 at 01:03:41PM +0000, Robin Murphy wrote: > > > External email: Use caution opening links or attachments > > > > > > > > > On 2023-03-09 10:53, Nicolin Chen wrote: > > > > This is used to forward the host IDR values to the user space, so the > > > > hypervisor and the guest VM can learn about the underlying hardware's > > > > capabilities. > > > > > > > > Also, set the driver_type to IOMMU_HW_INFO_TYPE_ARM_SMMUV3 to pass the > > > > corresponding type sanity in the core. > > > > > > > > Signed-off-by: Nicolin Chen > > > > --- > > > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 +++++++++++++++++++++ > > > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ > > > > include/uapi/linux/iommufd.h | 14 ++++++++++++ > > > > 3 files changed, 41 insertions(+) > > > > > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > > index f2425b0f0cd6..c1aac695ae0d 100644 > > > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > > @@ -2005,6 +2005,29 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) > > > > } > > > > } > > > > > > > > +static void *arm_smmu_hw_info(struct device *dev, u32 *length) > > > > +{ > > > > + struct arm_smmu_master *master = dev_iommu_priv_get(dev); > > > > + struct iommu_hw_info_smmuv3 *info; > > > > + void *base_idr; > > > > + int i; > > > > + > > > > + if (!master || !master->smmu) > > > > + return ERR_PTR(-ENODEV); > > > > + > > > > + info = kzalloc(sizeof(*info), GFP_KERNEL); > > > > + if (!info) > > > > + return ERR_PTR(-ENOMEM); > > > > + > > > > + base_idr = master->smmu->base + ARM_SMMU_IDR0; > > > > + for (i = 0; i <= 5; i++) > > > > + info->idr[i] = readl_relaxed(base_idr + 0x4 * i); > > > > > > You need to take firmware overrides etc. into account here. In > > > particular, features like BTM may need to be hidden to work around > > > errata either in the system integration or the SMMU itself. It isn't > > > reasonable to expect every VMM to be aware of every erratum and > > > workaround, and there may even be workarounds where we need to go out of > > > our way to prevent guests from trying to use certain features in order > > > to maintain correctness at S2. > > > > We can add a bit of overrides after this for errata, perhaps? > > > > I have some trouble with finding the errata docs. Would it be > > possible for you to direct me to it with a link maybe? > > The key Arm term is "Software Developer Errata Notice", or just SDEN. > Here's the ones for MMU-600 and MMU-700: > > https://developer.arm.com/documentation/SDEN-946810/latest/ This page shows "Arm CoreLink MMU-600 System Memory Management Unit Software Developer Errata Notice" but the downloaded file is "Arm CoreLink CI-700 Coherent Interconnect" errata notice. And I don't quite understand what it's about. > https://developer.arm.com/documentation/SDEN-1786925/latest/ Yea, this one I got an "MMU-700 System Memory Management Unit" SMMU errata file that I can read and understand. > Note that until now it has been extremely fortunate that in pretty much > every case Linux either hasn't supported the affected feature at all, or > has happened to avoid meeting the conditions. Once we do introduce > nesting support that all goes out the window (and I'll have to think > more when reviewing new errata in future...) > > I've been putting off revisiting all the existing errata to figure out > what we'd need to do until new nesting patches appeared, so I'll try to > get to that soon now. I think in many cases it's likely to be best to > just disallowing nesting entirely on affected implementations. Do we have already a list of "affected implementations"? Or, we would need to make such a list now? In a latter case, can these affected implementations be detected from their IRD0-5 registers, so that we can simply do something in hw_info()? Thanks Nic