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From:   Vasily Khoruzhick <anarsoul@gmail.com>
Date:   Wed, 15 Mar 2023 17:16:30 -0700
Message-ID: <CA+E=qVei7T4T0FWhdUFnr5JbCWSgFbGLcmU2OHxx54yvnNR6mw@mail.gmail.com>
Subject: Re: [PATCH 4/5] arm64: dts: rockchip: fix gmac support for NanoPi R5S
To:     Tianling Shen <cnsztl@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Jagan Teki <jagan@amarulasolutions.com>,
        Peter Geis <pgwipeout@gmail.com>, Andy Yan <andyshrk@163.com>,
        Brian Norris <briannorris@chromium.org>,
        Chris Morgan <macromorgan@hotmail.com>,
        Sebastian Reichel <sebastian.reichel@collabora.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Michael Riesch <michael.riesch@wolfvision.net>,
        Maya Matuszczyk <maccraft123mc@gmail.com>,
        Andrew Powers-Holmes <aholmes@omnom.net>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
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On Wed, Mar 15, 2023 at 9:02=E2=80=AFAM Tianling Shen <cnsztl@gmail.com> wr=
ote:
>
> - Changed phy-mode to rgmii.
>
> - Fixed pull type in pinctrl for gmac0.
>
> - Removed duplicate properties in mdio node.
>   These properties are defined in the gmac0 node already.
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/ar=
m64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> index e9adf5e66529..2a1118f15c29 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> @@ -57,7 +57,7 @@
>         assigned-clock-rates =3D <0>, <125000000>;
>         clock_in_out =3D "output";
>         phy-handle =3D <&rgmii_phy0>;
> -       phy-mode =3D "rgmii-id";
> +       phy-mode =3D "rgmii";
>         pinctrl-names =3D "default";
>         pinctrl-0 =3D <&gmac0_miim
>                      &gmac0_tx_bus2
> @@ -79,9 +79,6 @@
>                 reg =3D <1>;
>                 pinctrl-0 =3D <&eth_phy0_reset_pin>;
>                 pinctrl-names =3D "default";
> -               reset-assert-us =3D <10000>;
> -               reset-deassert-us =3D <50000>;
> -               reset-gpios =3D <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;

Hmm, I don't see RK_PC4 being used anywhere else. gmac0 has RK_PC5 as
snsp,reset-gpio. So it essentially drops reset for the PHY. Is it
expected?

>         };
>  };
>
> @@ -115,7 +112,7 @@
>  &pinctrl {
>         gmac0 {
>                 eth_phy0_reset_pin: eth-phy0-reset-pin {
> -                       rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pu=
ll_down>;
> +                       rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pu=
ll_up>;
>                 };
>         };
>
> --
> 2.17.1
>