From:   David Yang <mmyangfl@gmail.com>
To:     mmyangfl@gmail.com
Cc:     Wei Xu <xuwei5@hisilicon.com>,
        Russell King <linux@armlinux.org.uk>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/3] ARM: hisi: Add S5 IO map
Date:   Thu, 16 Mar 2023 13:19:34 +0800
Message-Id: <20230316051936.1775033-3-mmyangfl@gmail.com>
In-Reply-To: <20230316051936.1775033-1-mmyangfl@gmail.com>
References: <20230316051936.1775033-1-mmyangfl@gmail.com>
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Hisilion S5 platform supports ARM Cortex-A7 processors.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
 arch/arm/mach-hisi/hisilicon.c | 37 ++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 9f56b0f56..f9109df8c 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -83,3 +83,40 @@ DT_MACHINE_START(S40, "Hisilicon S40 (Flattened Device Tree)")
 	.map_io		= s40_map_io,
 	.dt_compat	= s40_compat,
 MACHINE_END
+
+#define S5_IOCH2_PHYS_BASE		0xff000000
+#define S5_IOCH2_VIRT_BASE		0xfb000000
+#define S5_IOCH2_SIZE			0x00430000
+
+static struct map_desc s5_io_desc[] __initdata = {
+	{
+		.pfn		= __phys_to_pfn(S5_IOCH2_PHYS_BASE),
+		.virtual	= S5_IOCH2_VIRT_BASE,
+		.length		= S5_IOCH2_SIZE,
+		.type		= MT_DEVICE,
+	},
+	{
+		.pfn		= __phys_to_pfn(S40_IOCH1_PHYS_BASE),
+		.virtual	= S40_IOCH1_VIRT_BASE,
+		.length		= S40_IOCH1_SIZE,
+		.type		= MT_DEVICE,
+	},
+};
+
+static void __init s5_map_io(void)
+{
+	debug_ll_io_init();
+	iotable_init(s5_io_desc, ARRAY_SIZE(s5_io_desc));
+}
+
+static const char *const s5_compat[] __initconst = {
+	"hisilicon,hi3716cv200",
+	"hisilicon,hi3716mv410",
+	"hisilicon,hi3798mv100",
+	NULL,
+};
+
+DT_MACHINE_START(S5, "Hisilicon S5 (Flattened Device Tree)")
+	.map_io		= s5_map_io,
+	.dt_compat	= s5_compat,
+MACHINE_END
-- 
2.39.2