Message-ID: <69f0d161-e473-37dc-13a9-c81ec9145de2@yandex-team.ru>
Date:   Thu, 16 Mar 2023 08:51:15 +0300
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Subject: Re: [PATCH] kvm/x86: actually verify that reading MSR_IA32_UCODE_REV
 succeeds
To:     Sean Christopherson <seanjc@google.com>
Cc:     Paolo Bonzini <pbonzini@redhat.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
        "H. Peter Anvin" <hpa@zytor.com>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20230315195109.580333-1-d-tatianin@yandex-team.ru>
 <ZBInlO18ZlClLbHp@google.com>
Content-Language: en-US
From:   Daniil Tatianin <d-tatianin@yandex-team.ru>
In-Reply-To: <ZBInlO18ZlClLbHp@google.com>
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On 3/15/23 11:16 PM, Sean Christopherson wrote:
> On Wed, Mar 15, 2023, Daniil Tatianin wrote:
>> ...and return KVM_MSR_RET_INVALID otherwise.
>>
>> Found by Linux Verification Center (linuxtesting.org) with the SVACE
>> static analysis tool.
>>
>> Fixes: cd28325249a1 ("KVM: VMX: support MSR_IA32_ARCH_CAPABILITIES as a feature MSR")
>> Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru>
>> ---
>>   arch/x86/kvm/x86.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
>> index 7713420abab0..7de6939fc371 100644
>> --- a/arch/x86/kvm/x86.c
>> +++ b/arch/x86/kvm/x86.c
>> @@ -1661,7 +1661,8 @@ static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
>>   		msr->data = kvm_caps.supported_perf_cap;
>>   		break;
>>   	case MSR_IA32_UCODE_REV:
>> -		rdmsrl_safe(msr->index, &msr->data);
>> +		if (rdmsrl_safe(msr->index, &msr->data))
>> +			return KVM_MSR_RET_INVALID;
> 
> This is unnecessary and would arguably break KVM's ABI.  KVM unconditionally emulates
> MSR_IA32_UCODE_REV in software and rdmsrl_safe() zeros the result on a fault (see
> ex_handler_msr()).  '0' is a legitimate ucode revid and a reasonable fallback for
> a theoretical (virtual) CPU that doesn't support the MSR.

I see, thanks for the explanation!