Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E698C7618A for ; Thu, 16 Mar 2023 08:12:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231152AbjCPIMq (ORCPT ); Thu, 16 Mar 2023 04:12:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229758AbjCPIM0 (ORCPT ); Thu, 16 Mar 2023 04:12:26 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CFE0B4F51 for ; Thu, 16 Mar 2023 01:12:11 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id y2so878694pjg.3 for ; Thu, 16 Mar 2023 01:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678954327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4qWXiXHbprZdRw+FBFkQgRot6Gb1s+rxs+MQA1ld6Qs=; b=QFLcxan8pYvVWTcYbT6PxIK/s5w+dsTX4qrlzwYpTWMmejni3tZXkOTvzwTdQ08ojF 0/+OyS88A4AnHazDyBC1qGIVwM+fGmao36MRl0Ct2fhQhlRBubsEbdntgxgYA0HiEMts EAlBAuOZ98y45dVMb70hOsncPf2W/8Ieke0rFk93IANWe9ae8ff43sNAqBiRnxs1EWng aX7Q1AyaPUOs1dJPzrTorubK87dW5exbqfIH63L5mPHrpgIuHdK42MNr8y4OWG0lxdpe XLjSRVHuNBDr06G5VzJl96QTZoeIiYmi/LTiYIayRJW2P04ih+fujr+Ocqt1J1onQo00 L/4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678954327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4qWXiXHbprZdRw+FBFkQgRot6Gb1s+rxs+MQA1ld6Qs=; b=idSnmLfKxeADZQOepYaANX2vae0UYmWIrT5wZxztD7hiTheVsgjUNEYg6SdBp7dGLG zjP1iRrBjyoWgJ1H5f/71IZ/DVDKRNL5fhimG/Yz9Oer72NhduvIK95qzr1mcLSBG1oy xVhJKPMYNxjNXTCWAC589QOBHTQbgZZMoUneq2pQS3mLIYJiyIc6ib9yZr/4mf5LA+Ki MSnwpcNY6yLkCs7rGaeCL8z2fvCL+ocQZwAJwXiPlY0cdMHJDCUJ0XzIev8HDg4MvxEk /LUvTR8IU8B9R2CDwFThzA+njqKCsg+P2GfKMPookcyOoJHltgg9owLlWX9uKy2WRlxj ILDA== X-Gm-Message-State: AO0yUKXy/NNlmueCQneNvkYlV6LOtMPKOnYpLzIQtTOd9eVlXLDbd6kr DY1mFNwiXAdFed/UKhUJ9NxA X-Google-Smtp-Source: AK7set8cb+VRqi1fxNLlPk8XeD8xgJci7tEr/5MVQAAFhrt4iIoOvCyy3Xl0quh+dcPdZGBCxyTT/g== X-Received: by 2002:a05:6a20:3d15:b0:d6:4003:e386 with SMTP id y21-20020a056a203d1500b000d64003e386mr3694528pzi.48.1678954327094; Thu, 16 Mar 2023 01:12:07 -0700 (PDT) Received: from localhost.localdomain ([117.207.30.24]) by smtp.gmail.com with ESMTPSA id 13-20020aa7910d000000b005d9984a947bsm4804422pfh.139.2023.03.16.01.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 01:12:06 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v5 08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 Date: Thu, 16 Mar 2023 13:41:06 +0530 Message-Id: <20230316081117.14288-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230316081117.14288-1-manivannan.sadhasivam@linaro.org> References: <20230316081117.14288-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 72 +++++++------------------- 1 file changed, 19 insertions(+), 53 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 10e792604042..14373d591ed1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -145,11 +145,9 @@ #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 struct qcom_pcie_resources_1_0_0 { - struct clk *iface; - struct clk *aux; - struct clk *master_bus; - struct clk *slave_bus; + struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; struct reset_control *core; struct regulator *vdda; }; @@ -439,26 +437,20 @@ static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + int ret; res->vdda = devm_regulator_get(dev, "vdda"); if (IS_ERR(res->vdda)) return PTR_ERR(res->vdda); - res->iface = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->aux = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux)) - return PTR_ERR(res->aux); - - res->master_bus = devm_clk_get(dev, "master_bus"); - if (IS_ERR(res->master_bus)) - return PTR_ERR(res->master_bus); + res->clks[0].id = "iface"; + res->clks[1].id = "aux"; + res->clks[2].id = "master_bus"; + res->clks[3].id = "slave_bus"; - res->slave_bus = devm_clk_get(dev, "slave_bus"); - if (IS_ERR(res->slave_bus)) - return PTR_ERR(res->slave_bus); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; res->core = devm_reset_control_get_exclusive(dev, "core"); return PTR_ERR_OR_ZERO(res->core); @@ -469,10 +461,7 @@ static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; reset_control_assert(res->core); - clk_disable_unprepare(res->slave_bus); - clk_disable_unprepare(res->master_bus); - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->aux); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_disable(res->vdda); } @@ -489,46 +478,23 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) return ret; } - ret = clk_prepare_enable(res->aux); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_res; - } - - ret = clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_aux; - } - - ret = clk_prepare_enable(res->master_bus); - if (ret) { - dev_err(dev, "cannot prepare/enable master_bus clock\n"); - goto err_iface; - } - - ret = clk_prepare_enable(res->slave_bus); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable slave_bus clock\n"); - goto err_master; + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_reset; } ret = regulator_enable(res->vdda); if (ret) { dev_err(dev, "cannot enable vdda regulator\n"); - goto err_slave; + goto err_disable_clks; } return 0; -err_slave: - clk_disable_unprepare(res->slave_bus); -err_master: - clk_disable_unprepare(res->master_bus); -err_iface: - clk_disable_unprepare(res->iface); -err_aux: - clk_disable_unprepare(res->aux); -err_res: + +err_disable_clks: + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); +err_assert_reset: reset_control_assert(res->core); return ret; -- 2.25.1