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Thu, 16 Mar 2023 04:33:19 -0500 From: Harini Katakam To: , , , CC: , , , , , , Subject: [PATCH] dmaengine: zynqmp_dma: Sync DMA and coherent masks Date: Thu, 16 Mar 2023 15:03:18 +0530 Message-ID: <20230316093318.6722-1-harini.katakam@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT086:EE_|PH7PR12MB6717:EE_ X-MS-Office365-Filtering-Correlation-Id: 17502291-9e6c-4bed-a7b5-08db26017cc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U1jxUmnvfDsksQKKRt6FkzKoigmld32JDIFQY6XGZaLLwZD9m+Nnd294lLbPZzSgC9fiZzctaX7dWsvJ+bdwvuiGrnBv0RLZzQMZ4WeKA9qUq5Hyv5WRmPSAiinkGjyEDh6667AlU7WbmJ8CCC43jRCxtnXhtBfbN0pkKXkgU0u84mdeeKl0zt9MMd9i0LkVU7cI8ND9J1wotAqZ2cglVOg0G4SR7fhnWEo8ckhhXrUx+kDm9LuVFoa9EFNwSSXnL7yi+OsRZugGyRCmlxLmC5l/BXk7a9WUiw407CNbmqP8EmwFv+XumDVI1ZowhrvVXPAAUKNaS0ZzXwAcdbciMkfSXFRI4Ii8/QsIX6RJ2SWFNtyP6WzSP6CwumN82i9tFFtWAKsEe18+lMPjeUqqbvtFt5LBqWmKduZPubwWKiUzmTSlF1EeqhTX7LSUUrNB/bmQFpmfOJ7RZeUGDh5alXHTIsYR23FOgC+LAoAfToVpFruFQ62hG9GzsisFg2h0+fdVa340QoJHUyivn19g2yeTqFE3EOvjpTqzP3fZn3mqLXuyrse8Wq5IwlWLAOv6QGDKyAQzxgVtkyhhXhjlJYF6wwLU2NVV+WN242RhaLGKPTDSNA86SUooSiQoY4xYnBVXVN94qnq1OvBgfWj7cipFFvTNcVPRL2bfTSgoYTLfcFxMz0hbRcX7NGBZI3IwcsU+GHI8BDn+1xh2wsVm2PcfNMuxc9zgJbMzv0ulIEU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(346002)(396003)(136003)(376002)(39860400002)(451199018)(46966006)(36840700001)(40470700004)(4744005)(41300700001)(8936002)(5660300002)(2906002)(44832011)(81166007)(82740400003)(36756003)(36860700001)(356005)(82310400005)(86362001)(478600001)(8676002)(70206006)(70586007)(110136005)(316002)(40460700003)(2616005)(40480700001)(1076003)(4326008)(426003)(47076005)(83380400001)(54906003)(26005)(186003)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2023 09:33:23.1842 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17502291-9e6c-4bed-a7b5-08db26017cc8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT086.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6717 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Align ZDMA DMA as well as coherent memory masks to 44 bit. This is required when using >32 bit memory regions. Signed-off-by: Harini Katakam --- drivers/dma/xilinx/zynqmp_dma.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 3f4ee3954384..34d7d20ffc09 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -1051,7 +1051,11 @@ static int zynqmp_dma_probe(struct platform_device *pdev) zdev->dev = &pdev->dev; INIT_LIST_HEAD(&zdev->common.channels); - dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); + if (ret) { + dev_err(&pdev->dev, "DMA not available for address range\n"); + return ret; + } dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask); p = &zdev->common; -- 2.17.1