Date:   Thu, 16 Mar 2023 11:35:57 +0100
From:   Michal Kubiak <michal.kubiak@intel.com>
To:     Bartosz Wawrzyniak <bwawrzyn@cisco.com>
CC:     <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
        <pabeni@redhat.com>, <nicolas.ferre@microchip.com>,
        <claudiu.beznea@microchip.com>, <netdev@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <xe-linux-external@cisco.com>,
        <danielwa@cisco.com>, <olicht@cisco.com>, <mawierzb@cisco.com>
Subject: Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than
 160MHz
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References: <20230316100339.1302212-1-bwawrzyn@cisco.com>
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On Thu, Mar 16, 2023 at 10:03:39AM +0000, Bartosz Wawrzyniak wrote:
> Currently macb sets clock divisor for pclk up to 160 MHz.
> Function gem_mdc_clk_div was updated to enable divisor
> for higher values of pclk.
> 
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
> ---
>  drivers/net/ethernet/cadence/macb.h      | 2 ++
>  drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 14dfec4db8f9..c1fc91c97cee 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -692,6 +692,8 @@
>  #define GEM_CLK_DIV48				3
>  #define GEM_CLK_DIV64				4
>  #define GEM_CLK_DIV96				5
> +#define GEM_CLK_DIV128				6
> +#define GEM_CLK_DIV224				7
>  
>  /* Constants for MAN register */
>  #define MACB_MAN_C22_SOF			1
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 6e141a8bbf43..8708af6d25ed 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -2641,8 +2641,12 @@ static u32 gem_mdc_clk_div(struct macb *bp)
>  		config = GEM_BF(CLK, GEM_CLK_DIV48);
>  	else if (pclk_hz <= 160000000)
>  		config = GEM_BF(CLK, GEM_CLK_DIV64);
> -	else
> +	else if (pclk_hz <= 240000000)
>  		config = GEM_BF(CLK, GEM_CLK_DIV96);
> +	else if (pclk_hz <= 320000000)
> +		config = GEM_BF(CLK, GEM_CLK_DIV128);
> +	else
> +		config = GEM_BF(CLK, GEM_CLK_DIV224);
>  
>  	return config;
>  }

Hi,

The patch looks OK.

Thanks,
Michal

Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>

> -- 
> 2.33.0
>