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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id a9-20020a2eb549000000b00295735991edsm1261639ljn.38.2023.03.16.07.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 07:13:08 -0700 (PDT) From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:54 +0100 Subject: [PATCH v2 05/14] arm64: dts: qcom: sm6375: Add IMEM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230303-topic-sm6375_features0_dts-v2-5-708b8191f7eb@linaro.org> References: <20230303-topic-sm6375_features0_dts-v2-0-708b8191f7eb@linaro.org> In-Reply-To: <20230303-topic-sm6375_features0_dts-v2-0-708b8191f7eb@linaro.org> To: Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Rob Herring , Krzysztof Kozlowski , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678975978; l=952; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=XeByskUh4IJy5GUSRGVEOURhAeiNtSqMfR5ebBA6Oes=; b=mMAFk6AuU/gMpqPyPUUUhzoWQDrmjRlIU1ZiIzMYlaaCXfIpkR1Gf2xkYL/WskH9spuP5ffJlJOb H/ScjN/2BaU3hl3N5lADcQaDr/OLOi1WI32ZPyhUss9gyoU1iIa1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a node for the IMEM block on SM6375. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index de5882c0ff81..5a0abb7f7124 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1233,6 +1233,20 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + sram@c125000 { + compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; + reg = <0 0x0c125000 0 0x1000>; + ranges = <0 0 0x0c125000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; reg = <0 0x0c600000 0 0x100000>; -- 2.39.2