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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id c25-20020aa78c19000000b00623f72df4e2sm1132370pfd.203.2023.03.17.02.52.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Mar 2023 02:52:41 -0700 (PDT) Message-ID: <77b713f8-93bd-d0fa-d344-c8a4ec365c50@gmail.com> Date: Fri, 17 Mar 2023 17:52:37 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings Content-Language: en-US To: Krzysztof Kozlowski , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang References: <20230315072902.9298-1-ychuang570808@gmail.com> <20230315072902.9298-9-ychuang570808@gmail.com> <0ad8521d-90b9-29c7-62e6-2d65aa2a7a27@linaro.org> <00423efa-d4ca-5d76-d0b2-11853a49c5e9@gmail.com> From: Jacky Huang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Krzysztof, Thanks for your advice. On 2023/3/17 下午 05:13, Krzysztof Kozlowski wrote: > On 17/03/2023 04:47, Jacky Huang wrote: >>>> + >>>> + nuvoton,pll-mode: >>>> + description: >>>> + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, >>>> + EPLL, and VPLL in sequential. The operation mode value 0 is for >>>> + integer mode, 1 is for fractional mode, and 2 is for spread >>>> + spectrum mode. >>>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>>> + maxItems: 5 >>>> + items: >>>> + minimum: 0 >>>> + maximum: 2 >>> Why exactly this is suitable for DT? >> I will use strings instead. > I have doubts why PLL mode is a property of DT. Is this a board-specific > property? CA-PLL has mode 0 only. DDRPLL, APLL, EPLL, and VPLL have the same PLL design that supports integer mode, fractional mode, and spread spctrum mode. The PLL mode is controlled by clock controller register. I think it's not board-specific. >>>> + >>>> + nuvoton,sys: >>>> + description: >>>> + Phandle to the system management controller. >>>> + $ref: "/schemas/types.yaml#/definitions/phandle-array" >>> Drop quotes. >>> >>> You need here constraints, look for existing examples. >>> >> I would like to modify this as: >> >> >>   nuvoton,sys: >>     description: >>       Use to unlock and lock some clock controller registers. The lock >>       control register is in system controller. >>     $ref: /schemas/types.yaml#/definitions/phandle-array >>     items: >>       - items: >>           - description: phandle to the system controller. > In such case you do not have array. Just make it phandle and drop the items. > Thank you. So, I will rewrite it as   nuvoton,sys:     description:       Use to unlock and lock some clock controller registers. The lock       control register is in system controller.     $ref: /schemas/types.yaml#/definitions/phandle > > Best regards, > Krzysztof > Best regards, Jacky Huang