Message-ID: <f836d98d-bb3b-64a5-1598-1ef489e62fb6@starfivetech.com>
Date:   Fri, 17 Mar 2023 18:29:06 +0800
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Subject: Re: [PATCH v3 1/5] dt-bindings: phy: Add StarFive JH7110 USB/PCIe
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        Conor Dooley <conor@kernel.org>,
        "Vinod Koul" <vkoul@kernel.org>,
        Kishon Vijay Abraham I <kishon@kernel.org>,
        "Rob Herring" <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Pawel Laszczak <pawell@cadence.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Peter Chen <peter.chen@kernel.org>,
        Roger Quadros <rogerq@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>
CC:     <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-phy@lists.infradead.org>, <linux-usb@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>
References: <20230315104411.73614-1-minda.chen@starfivetech.com>
 <20230315104411.73614-2-minda.chen@starfivetech.com>
 <f7752f68-11a6-cbf4-2f28-1de4c7ff9da2@linaro.org>
From:   Minda Chen <minda.chen@starfivetech.com>
In-Reply-To: <f7752f68-11a6-cbf4-2f28-1de4c7ff9da2@linaro.org>
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Precedence: bulk


On 2023/3/17 16:39, Krzysztof Kozlowski wrote:
> On 15/03/2023 11:44, Minda Chen wrote:
>> Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
>> PCIe 2.0 phy can use as USB 3.0 PHY.
>> 
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> ---
>>  .../phy/starfive,jh7110-usb-pcie-phy.yaml     | 62 +++++++++++++++++++
>>  1 file changed, 62 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
>> new file mode 100644
>> index 000000000000..aa1c3fe93100
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
>> @@ -0,0 +1,62 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-pcie-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive USB 2.0 and PCIe 2.0 PHY
>> +
>> +maintainers:
>> +  - Minda Chen <minda.chen@starfivetech.com>
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - starfive,jh7110-usb-phy
>> +      - starfive,jh7110-pcie-phy
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  "#phy-cells":
>> +    const: 0
>> +
>> +  clocks:
>> +    items:
>> +      - description: usb 125m clock
>> +      - description: app 125m clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: 125m
>> +      - const: app_125
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - "#phy-cells"
>> +
> 
> It seems pci phy does not take these clocks, thus you should have
> allOf:if:then which will customize it per variant. Otherwise binding is
> incorrect for the pci.
> 
ok
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    phy@10200000 {
>> +      compatible = "starfive,jh7110-usb-phy";
>> +      reg = <0x10200000 0x10000>;
>> +      clocks = <&syscrg 95>,
>> +               <&stgcrg 6>;
>> +      clock-names = "125m", "app_125";
>> +      #phy-cells = <0>;
>> +    };
>> +
>> +    phy@10210000 {
>> +      compatible = "starfive,jh7110-pcie-phy";
>> +      reg = <0x10210000 0x10000>;
>> +      #phy-cells = <0>;
>> +    };
>> +
>> +    phy@10220000 {
>> +      compatible = "starfive,jh7110-pcie-phy";
>> +      reg = <0x10220000 0x10000>;
>> +      #phy-cells = <0>;
>> +    };
> 
> Drop duplicated examples. Keep usb and maybe one phy.
> 
ok, thanks
> Best regards,
> Krzysztof
>