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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?j+FXnK59TcM/ShptutH0T06DgPjuqdtU3MefTHacf+YsGr9VjeP0lttu0rC0?= =?us-ascii?Q?xTFrOQl4WE/OKQhPhkoLIJUyNHrqtvqBl2Z6viGpB301w+JEdn+XO+k49aNs?= =?us-ascii?Q?RQBvZZ40pDEYNhCE3eJcRv8ZOpHxVnkg+IZGtqiAWlzflLCWRxNM5r6OMq0m?= =?us-ascii?Q?L9nSOQqukYhwqkvfoIP8B0SJV9BokmV10jGQ0ahMlYe/iWByN+bLACaDX9EY?= =?us-ascii?Q?MRwThFcrELLGkTlm03PtuV6l0V6bo3roP5qieKF6wZbj8c9DhBxIT+GTp2vd?= =?us-ascii?Q?Cnh4PJCnl47JUD8gqIt40nhZzACCxS/SymiyrIiKIWh89e4zIxQdToy96XvN?= =?us-ascii?Q?5u7XdgIvK1U+kj52Y0D4ZELXpL9RkxL0hZ8ObxBm9XLdpMm/vxxmyUQQX1KZ?= =?us-ascii?Q?/GWsRn8kayjPrSgvptY26np1GCQdBTiBe123Ch0GsGDkXor3nB2xDt5fvhQL?= =?us-ascii?Q?SHz4ehAt1nHv+yOF+IQi8wcYKA7poLO68A/PMK+DpLiLgpJS3ySk0rPpKvqL?= =?us-ascii?Q?fR5VKPZUFFqjUDarZivodPF/btGVui4Oyrxti9w5tg+f+vhMkelwK6EQ8cYF?= =?us-ascii?Q?htr6S11asWghzeHjuAD8tDkVxhNsMM7zw+IaZUhTC58hJTA/QywQ6r6k8S88?= =?us-ascii?Q?dQ4zz2JLM5KK0hQXHduNZu7Trvcg8mYmlwRdrDNUyb7a4XteyMzyEszl38+B?= =?us-ascii?Q?8SKMplVg11Ld/tyj/s6gxw6onrW4qr/A7Gkm5nVXFdZopBjENMWGkXuoCfr3?= =?us-ascii?Q?sQoV2kyftVt8qDG0ED8Pk5tMB2hMmGL84P4J5OAx6CsFhrZ1xNNf5IjQFKEy?= =?us-ascii?Q?8EPZE9D9RQKGQAiLrJvBOmJF+W6xj3DSn/MqyPrIuL3UtbeFrStpJ7rBSnXp?= =?us-ascii?Q?KH9dUld6K4DUkpP+q+DKRyaB4nrJ/2kwKENkeyjPz5bQqIFfBGIUvME44wzl?= =?us-ascii?Q?DriUp8p+/+0e/J/8Y8LSyzEhvrRkeRHFUFYMXRj4gKUJAxGGzcg73t9LmXNR?= =?us-ascii?Q?PHQrU2OtP8djDSthCkSz+jZVML750pGycZHUg1L4Zwb7SeORaJdfmf1MH6u9?= =?us-ascii?Q?Talfy2V+731ZqYTQAJPndJpLf2/w1Dm9KSmYN92xBmCoYRdMFRfSZOdVRSkl?= =?us-ascii?Q?CLorL41dg1mKmE+/0wNHoMGZTGF9wPun2aLagAiCj0usvpMisfca6Rh1tOZq?= =?us-ascii?Q?95z2yiaO0Oe8gUlLVxYQKVx1antqZ/ucv8JaNpiR1YZb+gP7qhngq1FLAfnJ?= =?us-ascii?Q?gmqViBZe4E2/PLDOKS/o7RZtb1VG/kTsKRqBPUoYWR+9mR7wxoSDHAjUKkjC?= =?us-ascii?Q?e8hIJ9Y5ubCmhokt1y0s/TGnT2oC00g2+Ta+xYQf8AVljCYyKYDHLEvul0kg?= =?us-ascii?Q?RZlzgo6nG26nfUhZmf/sQlCSnWJxLzAClXBSlqAMneu039dB/YmMvOTNWJVC?= =?us-ascii?Q?NI/THD8h0/k0AHu//WBYY36rjlHVwmu/vlWlteM0tMc6HUJDm6rdlWH17HY9?= =?us-ascii?Q?JNWOkmzCIYF68aZ/0RJh7Lh6XBiF3ZroxTyzB/CcVekOoxvXNsLp7rwcwhmu?= =?us-ascii?Q?2UTGpsFYT3iC8r8LHHmYzb3ryzWnoPUUfPiO8oXk?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 95b84e31-29cd-4190-857d-08db26f6e442 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2023 14:50:03.9088 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wr4/iR5PhIhdFqWVwYH3at9ahmEg9nOZoHkz5a/bYDn4cqigJ17rmGRaJVHKMOJSbWcI0zI3KkD12Z49yYkqOQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8121 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 27, 2022 at 10:36:00AM -0700, Tony Luck wrote: > Extend the logic of handling Intel's corrected machine check interrupt > storms to AMD's threshold interrupts. > > First two patches are from Tony which cleans up the existing storm > handling for Intel and proposes per CPU per bank storm handling. > > Third and fourth patches do some cleanup and refactoring on the CMCI > storm handling in order to extend similar workaround for AMD's threshold > interrupt storms. These two patches could be merged into Tony's second > patch of CMCI storm mitigation. > > AMD's storm mitigation for threshold interrupts also relies on per CPU > per bank approach similar to Intel. But unlike CMCI storm handling it does > not set thresholds to reduce rate of interrupts on a storm. Rather it > turns off the interrupt on the current CPU and bank if there is a storm > and re-enables back the interrupts when the storm subsides. > > It is okay to turn off threshold interrupts on AMD systems as other error > severities continue to be handled even if the threshold interrupts are > turned off. Uncorrected errors will generate a #MC and deferred errors > have a unique separate deferred error interrupt. The final patch adds > support for handling threshold interrupt storms on AMD systems. > > Changes since v1: > > 1) Fix shift computation when keeping track of bank history. Shift > should be "1" when a storm is in progress (because polling once per > second). When a storm is not in progress shift should be based on > number of seconds since the bank was last checked. > > 2) Changed Smita's code in part 0003 to avoid use of a function pointer > (since the kernel is avoiding indirect branch points that might be > trainable for various Spectre-like issues). > > Smita Koralahalli (2): > x86/mce: Introduce mce_handle_storm() to deal with begin/end of storms > x86/mce: Handle AMD threshold interrupt storms > x86/mce: Move storm handling to core. > > Tony Luck (3): > x86/mce: Remove old CMCI storm mitigation code > x86/mce: Add per-bank CMCI storm mitigation > > arch/x86/kernel/cpu/mce/amd.c | 49 ++++++++ > arch/x86/kernel/cpu/mce/core.c | 139 +++++++++++++++++----- > arch/x86/kernel/cpu/mce/intel.c | 179 +++++++---------------------- > arch/x86/kernel/cpu/mce/internal.h | 33 ++++-- > 4 files changed, 230 insertions(+), 170 deletions(-) > > -- Hi Tony, Is there an updated version of this set? I can help review and test. Smita is focusing on other items at the moment. Thanks! -Yazen