Date:   Fri, 17 Mar 2023 16:02:06 +0000
From:   Catalin Marinas <catalin.marinas@arm.com>
To:     Kristina Martsenko <kristina.martsenko@arm.com>
Cc:     linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
        Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
        Oliver Upton <oliver.upton@linux.dev>,
        James Morse <james.morse@arm.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Zenghui Yu <yuzenghui@huawei.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Mark Brown <broonie@kernel.org>,
        Luis Machado <luis.machado@arm.com>,
        Vladimir Murzin <vladimir.murzin@arm.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 08/10] arm64: mops: handle single stepping after MOPS
 exception
Message-ID: <ZBSO/sWK1IGkoOxj@arm.com>
References: <20230216160012.272345-1-kristina.martsenko@arm.com>
 <20230216160012.272345-9-kristina.martsenko@arm.com>
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On Thu, Feb 16, 2023 at 04:00:10PM +0000, Kristina Martsenko wrote:
> When a MOPS main or epilogue instruction is being executed, the task may
> get scheduled on a different CPU and restart execution from the prologue
> instruction. If the main or epilogue instruction is being single stepped
> then it makes sense to finish the step and take the step exception
> before starting to execute the next (prologue) instruction. So
> fast-forward the single step state machine when taking a MOPS exception.
> 
> This means that if a main or epilogue instruction is single stepped with
> ptrace, the debugger will sometimes observe the PC moving back to the
> prologue instruction. (As already mentioned, this should be rare as it
> only happens when the task is scheduled to another CPU during the step.)
> 
> This also ensures that perf breakpoints count prologue instructions
> consistently (i.e. every time they are executed), rather than skipping
> them when there also happens to be a breakpoint on a main or epilogue
> instruction.
> 
> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>