Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C34AEC7618A for ; Fri, 17 Mar 2023 16:52:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229888AbjCQQwb (ORCPT ); Fri, 17 Mar 2023 12:52:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229735AbjCQQw2 (ORCPT ); Fri, 17 Mar 2023 12:52:28 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7435B04B0; Fri, 17 Mar 2023 09:52:27 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32HEoEtL005684; Fri, 17 Mar 2023 16:52:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=xCuWvkMp0B6+iqZ+vQsgEhbCvhrCXKAn0TjlGV9iRP0=; b=n112tR9ckVyG8DqeqT2hU+3LiPuE/mpXLI5a6mx7HHfrrbGKTnaOJypMnyJoN5bQOuMA LY2kZlxrIC0TPfjfsPTIwI0CERRGiOvyOzcGnHv9PWnNpAuFKqi//zUDLEy3UNrv2i1/ la9ZAAAMp0NxasGlEZSIcyEAcdT+RBg094avZBPPcRt5Mw4GbJkGKRorPu20OcaO9e0l guT/jLx14kjwwyaziIhTG6k8hCRLiGGIGv2evZrSzvGTJpwxvONFwJkV05q86eAyt7eR DcBm34i+/8y7Oq9lVfQKuYuCqkI6TwzV1jdDO2ypAVO2VdlcUWEHZE3eXAR8tDQvhW5x tg== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pctap8hcw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Mar 2023 16:52:24 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32HGqOiX029384 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Mar 2023 16:52:24 GMT Received: from [10.216.13.67] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 17 Mar 2023 09:52:21 -0700 Message-ID: Date: Fri, 17 Mar 2023 22:22:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v3 1/5] firmware: qcom_scm: provide a read-modify-write function Content-Language: en-US To: , , , CC: , , References: <1679070482-8391-1-git-send-email-quic_mojha@quicinc.com> <1679070482-8391-2-git-send-email-quic_mojha@quicinc.com> From: Mukesh Ojha In-Reply-To: <1679070482-8391-2-git-send-email-quic_mojha@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZnKBHWmR_DoV9ortHLJ0CwnZadjwTgOX X-Proofpoint-GUID: ZnKBHWmR_DoV9ortHLJ0CwnZadjwTgOX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-17_10,2023-03-16_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=720 clxscore=1015 mlxscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303170113 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/17/2023 9:57 PM, Mukesh Ojha wrote: > It was released by Srinivas K. that there is a need of Typo: s/released/realized -- Mukesh > read-modify-write scm exported function so that it can > be used by multiple clients. > > Let's introduce qcom_scm_io_update_field() which masks > out the bits and write the passed value to that > bit-offset. Subsequent patch will use this function. > > Suggested-by: Srinivas Kandagatla > Signed-off-by: Mukesh Ojha > --- > drivers/firmware/qcom_scm.c | 15 +++++++++++++++ > include/linux/firmware/qcom/qcom_scm.h | 2 ++ > 2 files changed, 17 insertions(+) > > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c > index 3e020d1..aca2556 100644 > --- a/drivers/firmware/qcom_scm.c > +++ b/drivers/firmware/qcom_scm.c > @@ -407,6 +407,21 @@ int qcom_scm_set_remote_state(u32 state, u32 id) > } > EXPORT_SYMBOL(qcom_scm_set_remote_state); > > +int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask, unsigned int val) > +{ > + unsigned int old, new; > + int ret; > + > + ret = qcom_scm_io_readl(addr, &old); > + if (ret) > + return ret; > + > + new = (old & ~mask) | val; > + > + return qcom_scm_io_writel(addr, new); > +} > +EXPORT_SYMBOL(qcom_scm_io_update_field); > + > static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) > { > struct qcom_scm_desc desc = { > diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h > index 1e449a5..203a781 100644 > --- a/include/linux/firmware/qcom/qcom_scm.h > +++ b/include/linux/firmware/qcom/qcom_scm.h > @@ -84,6 +84,8 @@ extern bool qcom_scm_pas_supported(u32 peripheral); > > extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); > extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); > +extern int qcom_scm_io_update_field(phys_addr_t addr, unsigned int mask, > + unsigned int val); > > extern bool qcom_scm_restore_sec_cfg_available(void); > extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);