From:   Colin Foster <colin.foster@in-advantage.com>
To:     linux-phy@lists.infradead.org, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Russell King <linux@armlinux.org.uk>,
        Kishon Vijay Abraham I <kishon@kernel.org>,
        Vinod Koul <vkoul@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Eric Dumazet <edumazet@google.com>,
        "David S. Miller" <davem@davemloft.net>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Andrew Lunn <andrew@lunn.ch>, UNGLinuxDriver@microchip.com,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Claudiu Manoil <claudiu.manoil@nxp.com>,
        Vladimir Oltean <vladimir.oltean@nxp.com>,
        Lee Jones <lee@kernel.org>
Subject: [PATCH v2 net-next 5/9] net: mscc: ocelot: expose serdes configuration function
Date:   Fri, 17 Mar 2023 11:54:11 -0700
Message-Id: <20230317185415.2000564-6-colin.foster@in-advantage.com>
In-Reply-To: <20230317185415.2000564-1-colin.foster@in-advantage.com>
References: <20230317185415.2000564-1-colin.foster@in-advantage.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?E+WYB3cAJxRxI+48ynucso5uUGtkQk0GHVFWyQrc1Lqo12mPs3yCiTUnWqm7?=
 =?us-ascii?Q?wA9pKYnbFJl1mw1axv8oJXRrsgqqaHLjC/FvfBzXPBNv+J+NRymYkE47jiFI?=
 =?us-ascii?Q?KVF+DW4HT8L68bnwQDfjlgTZDqr1CB3gG4It8tWyDC2Azj6swWR32H+vdQ2y?=
 =?us-ascii?Q?7Q5x7fz4x0/VbVKmPvVR9vqsQJ4sqeg9FlVZVDXanvfGbuGoOG9TDOQYASb0?=
 =?us-ascii?Q?VIwtsyKD5/3tYU1CLYl+JXXqbbJ+ItIU/7YwKW3WK4ecWibTwhUYVEkzMtt8?=
 =?us-ascii?Q?bR+X2ZR4k4H7LlFbTsm73j5XzIeeAZDh2I2fWvP9sXm/P5HwePeVcTXHq4Oy?=
 =?us-ascii?Q?t1m1bpBNwo9hFVcjPJjDgA4riUVzQav7m0y6Y0jnUoNEslXQ7pFitw9Wd1GP?=
 =?us-ascii?Q?R5kjGj8ZRGeJLtnNyM7h8/UkqeaKAptC3cmvV27N7gyrPqrtMXMlmNfIyUCW?=
 =?us-ascii?Q?YiOX+tjWZb5wnpBob4kiVUrdxdoNnJI7PAKQ+7YqG46bX+SNh61EJolT8H4/?=
 =?us-ascii?Q?Wg3va/7QjAmAZ6c9XqWBvd3a7pRmkuNXe95V4sRcPP2tWe5hpXQDfjn0sTMk?=
 =?us-ascii?Q?c3tplNSdjR/GczXYxbpNBrpuX+aJUDjq3xnnPEZRwdQU/S6xRQxjq2bIXYp/?=
 =?us-ascii?Q?LK9IyEGwCwMRF7RNYqj9nAE2Gz0piTwYKSyR1bjXYcveWRbHQoTX4tPcJo0a?=
 =?us-ascii?Q?jnxTURjpghial9jnY07cLhLg3o0OI17r2nrcqpyoBnxI5r2RROqLIM5K2jqu?=
 =?us-ascii?Q?e/odV+hMeMEqjjVBItaLZDSMTCg16fQ9T2eFxlHKNOXwLUoX2j9gK4ig9o5L?=
 =?us-ascii?Q?TGzGrEmnsgx9mgzZbJwHbIRC4MxFS40lnCJ9qV2oLm9XPRtzf+5Bp+BZHAKj?=
 =?us-ascii?Q?qr1BY8ZxHhR3Kvjdzkm6jCzgDam0wdBDOawNU8ZVAlixI7XzGeJStQ/monlt?=
 =?us-ascii?Q?UrH/lQRj4XIWG0eR5isevqYO13dVK7eQGCfigaEqJwdN+DoMKLl0ReOpUuOa?=
 =?us-ascii?Q?P3y9s454Z5wIRBy/j3rCvAd32N3Oe5k8MD3m9n7boZsFa35XLykWbjH6Hbmx?=
 =?us-ascii?Q?7JOIdcQ5bArcMe0nRvefnDXK9KfqwwCW7hyfRwnnCcB83cYZyIdoHOrMQW7M?=
 =?us-ascii?Q?BWYolJJQ1nDUKDPhjJdEj4CAVXi1E5Ki1MCUG3Ds+A3nTEp2ZIUhlzW11yP+?=
 =?us-ascii?Q?VSayFAq9L8UTqCwO3ncqASeG/rYR/u+1Naaxp3LH1SXTji4m3XjsIp5n3p/b?=
 =?us-ascii?Q?D1IyrtC8vNv8vkYRvnjStSTjjPdVNpHC7gV2niTqyHuZqsAuDd898BNtTMlv?=
 =?us-ascii?Q?5FO+TLiNKa3bo5qtWf+vcvvCAQFXZo7kPWWrvnNJL2jEEWoyOCeSDW+DuQlK?=
 =?us-ascii?Q?fV4YiPlrVo9zmFR0xW/zlr4xnS7xXK8dglc2QH3giCKPTvWltp0jrnXSez5I?=
 =?us-ascii?Q?3NgiOOI1VI3PGPjnTa052a7q3G5rYl3ppkX3am0CCjIHP8PAolhIfUgf3qR/?=
 =?us-ascii?Q?99W6qjXACaYaDDETcUU8P2xX+fBizLDh0qHPCKGFUjfZ36CWhK2BXQeq49uH?=
 =?us-ascii?Q?cKnVYlWJtto1oVf+TfcCvyMEc4y3pQg3jDCq+61zqIT8xdG/QMgEp5ttxez7?=
 =?us-ascii?Q?ZNydDIbFKfDc6nCCz6k8sdU=3D?=
X-OriginatorOrg: in-advantage.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 9c9bedf8-eb8f-4d17-e5b8-08db27190d44
X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2023 18:54:35.5372
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: V3SiKB1XFAX9tMwkTPhlL28oNOLrT/XVwQyU29S6oHYMALgVlSMEKtRSSJ/EK8X/fEzpvaem0DhlfZ/LI6q4LV1f4vJp7CL+JEdGOyoYd5c=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR10MB5959
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

During chip initialization, ports that use SGMII / QSGMII to interface to
external phys need to be configured on the VSC7513 and VSC7514. Expose this
configuration routine, so it can be used by DSA drivers.

Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
---

v2
    * New patch

---
 drivers/net/ethernet/mscc/ocelot.c     | 40 ++++++++++++++++++++++++++
 drivers/net/ethernet/mscc/ocelot_net.c | 29 ++-----------------
 include/soc/mscc/ocelot.h              |  4 +++
 3 files changed, 47 insertions(+), 26 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 8292e93a3782..1502bb2c8ea7 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -7,6 +7,7 @@
 #include <linux/dsa/ocelot.h>
 #include <linux/if_bridge.h>
 #include <linux/iopoll.h>
+#include <linux/phy/phy.h>
 #include <soc/mscc/ocelot_hsio.h>
 #include <soc/mscc/ocelot_vcap.h>
 #include "ocelot.h"
@@ -809,6 +810,45 @@ static int ocelot_port_flush(struct ocelot *ocelot, int port)
 	return err;
 }
 
+int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
+				 struct device_node *portnp)
+{
+	struct ocelot_port *ocelot_port = ocelot->ports[port];
+	struct device *dev = ocelot->dev;
+	int err;
+
+	/* Ensure clock signals and speed are set on all QSGMII links */
+	if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII)
+		ocelot_port_rmwl(ocelot_port, 0,
+				 DEV_CLOCK_CFG_MAC_TX_RST |
+				 DEV_CLOCK_CFG_MAC_RX_RST,
+				 DEV_CLOCK_CFG);
+
+	if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) {
+		struct phy *serdes = of_phy_get(portnp, NULL);
+
+		if (IS_ERR(serdes)) {
+			err = PTR_ERR(serdes);
+			dev_err_probe(dev, err,
+				      "missing SerDes phys for port %d\n",
+				      port);
+			return err;
+		}
+
+		err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET,
+				       ocelot_port->phy_mode);
+		of_phy_put(serdes);
+		if (err) {
+			dev_err(dev, "Could not SerDes mode on port %d: %pe\n",
+				port, ERR_PTR(err));
+			return err;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes);
+
 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
 			       unsigned int link_an_mode,
 			       const struct phylink_link_state *state)
diff --git a/drivers/net/ethernet/mscc/ocelot_net.c b/drivers/net/ethernet/mscc/ocelot_net.c
index 590a2b2816ad..21a87a3fc556 100644
--- a/drivers/net/ethernet/mscc/ocelot_net.c
+++ b/drivers/net/ethernet/mscc/ocelot_net.c
@@ -1742,34 +1742,11 @@ static int ocelot_port_phylink_create(struct ocelot *ocelot, int port,
 		return -EINVAL;
 	}
 
-	/* Ensure clock signals and speed are set on all QSGMII links */
-	if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
-		ocelot_port_rmwl(ocelot_port, 0,
-				 DEV_CLOCK_CFG_MAC_TX_RST |
-				 DEV_CLOCK_CFG_MAC_RX_RST,
-				 DEV_CLOCK_CFG);
-
 	ocelot_port->phy_mode = phy_mode;
 
-	if (phy_mode != PHY_INTERFACE_MODE_INTERNAL) {
-		struct phy *serdes = of_phy_get(portnp, NULL);
-
-		if (IS_ERR(serdes)) {
-			err = PTR_ERR(serdes);
-			dev_err_probe(dev, err,
-				      "missing SerDes phys for port %d\n",
-				      port);
-			return err;
-		}
-
-		err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, phy_mode);
-		of_phy_put(serdes);
-		if (err) {
-			dev_err(dev, "Could not SerDes mode on port %d: %pe\n",
-				port, ERR_PTR(err));
-			return err;
-		}
-	}
+	err = ocelot_port_configure_serdes(ocelot, port, portnp);
+	if (err)
+		return err;
 
 	priv = container_of(ocelot_port, struct ocelot_port_private, port);
 
diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h
index 87ade87d3540..d757b5e26d26 100644
--- a/include/soc/mscc/ocelot.h
+++ b/include/soc/mscc/ocelot.h
@@ -644,6 +644,7 @@ enum ocelot_tag_prefix {
 };
 
 struct ocelot;
+struct device_node;
 
 struct ocelot_ops {
 	struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
@@ -1111,6 +1112,9 @@ int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
 				   enum devlink_sb_pool_type pool_type,
 				   u32 *p_cur, u32 *p_max);
 
+int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
+				 struct device_node *portnp);
+
 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
 			       unsigned int link_an_mode,
 			       const struct phylink_link_state *state);
-- 
2.25.1