From:   Kevin Groeneveld <kgroeneveld@lenbrook.com>
To:     Mark Brown <broonie@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Cc:     Kevin Groeneveld <kgroeneveld@lenbrook.com>
Subject: [PATCH] spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3
Date:   Sat, 18 Mar 2023 18:21:32 -0400
Message-Id: <20230318222132.3373-1-kgroeneveld@lenbrook.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?OVBNV0ZodFZEK3FVb3Z2Nmgwcm1CV1czSlVqSmdqc2w1enhWTUF0U3czS2lj?=
 =?utf-8?B?bTA3TVMxUWY3aWFjbk5IMkVzRGJ4TFlIRFk2NHV6Q3hmRU93YUhlMjROYmI2?=
 =?utf-8?B?NzlJVk96MEhNTlJQemJjOVR4OFh6dURpVStSSGpCYkF6aWNlYkF5YlJJNzJQ?=
 =?utf-8?B?RDkxOFRpd2x6dFJBYVBFTDZKcTFuSEM0TDdPeFhDTVhSQkozeHZUMWttQUJT?=
 =?utf-8?B?UjBJZFZpdElwY2tkQzlxVjU0RTh3S2MwK3BuZHMrSnQ2bFFKUGZCMXNWbGtT?=
 =?utf-8?B?VEo1SHZHWTVvb1F4R2hCbnpyOFhIZVJ2S2tOajdvcVRNdDlqYlhMUTJkMkpk?=
 =?utf-8?B?cllLSVNXaU1WOVRxQjRDSG9XS0IwclkzU3J1aVdNOS9VN3R4QWRYTGE0bkNR?=
 =?utf-8?B?MzVNdjk3U2JobCtGbWtwdm5nLzFudmI0MEtaMGs2ZWFrUUtxdFk4eG9GMFVE?=
 =?utf-8?B?S3FUNU9OOUtMZi9OYUVIWTVnREE1Kyt1TnpSR21LazJMMXVnSDhoWDVwT2xD?=
 =?utf-8?B?citSSXlFU3BJeVMvTXVSSDhHMkR6YVI3cjhIanRKeTFuNldSalp3eUhVOXM3?=
 =?utf-8?B?dWdKTHpzL0FTMEV3cGdvVmsybmFsUXdURWRnVko3emtRQi8xNDVwSEtkNk5B?=
 =?utf-8?B?SHBQUi9GVm14WWdHU2NRSFpNZGxSU1RadFZyVjkraWt0N2hLZnZDd0xhZHkr?=
 =?utf-8?B?eFpTRGFJMlNmaGVFSTZoYkE5TitDeENEaFRxek5zcFI5ZlZFZXdKNFlYNVMy?=
 =?utf-8?B?Wi9KQUI0QkQyMzhqZTkwVTFqL2xUODBpRlRNMWE2c2ZGZ1dUNUV3YndoWitw?=
 =?utf-8?B?NlVUOVg4Zmx5amw0YkswTEEyd3JyQm5zWkRBaTlYdGtFZHZLYk1kWmZ6blZ3?=
 =?utf-8?B?TGx0VmxIZ1M0WUR3U1k3dS9HMG9UVGNDNEx0V1BMdWtPcElXUHVpNGNndkt0?=
 =?utf-8?B?VGpMU3lYWmlJcnkxTUVMODR5dTJ1RUZhTjVsUEtDOW1aTnk0U3QxV2R5K3J3?=
 =?utf-8?B?TXB3U0ZRbEtDMmlDNmppQjh1OU5yNkcvVUNvNC9sRzRUdkI2NEI2WGJyVnJz?=
 =?utf-8?B?dnpMMDBTanNJRzY5K1JVRzJoQ3FVamFveEpON1A3WjgrM3RGU09NNjlCNU1T?=
 =?utf-8?B?NGEwZC9zV3NKZ3I4Nlc5QU5icVZCYW0vK2JUR2xxRnNpa2RsbjBWMFk1Vkk0?=
 =?utf-8?B?ZFdrelBxc1VJTTI2aUU0c01UVTZ6Vzh4MHl4dnA4bzY5aXRKQ2RoYzFwSmNp?=
 =?utf-8?B?azZzamJZMzRodndVWEhuNWovWnhrbHg0c1lIY1dTNkZIS2UvTW1SbFBKbzl5?=
 =?utf-8?B?aDRJSk5IU3VoaGlVR29rRW1qL1gycHhWRlBIczRGaXdQWmlaM0VlWEtQYkRU?=
 =?utf-8?B?NURUalkyd3hNQWhIeXJBQmtlOVJHRVBSVWsyWm9HK1FxZXM4VThad202cUVm?=
 =?utf-8?B?ME8zeGVMTmZpOHhTOUtqOVV4aTV3cU4xTzdmMHk1djRUbkNDRzhXeURRMWo0?=
 =?utf-8?B?cWxCbU9oSlFLNnpBZ0Q3SWtSZ285M2Zta1dKU0RreDZ4QmJJNGM2WU9Rd0l0?=
 =?utf-8?B?VHBzbDFXY3NKdDFSMTlDenZFTk1WMkxoS2pTeTgya0c4T3A4OWwyYmYvdVQ1?=
 =?utf-8?B?ZzNHejhNNmQwdlVUdDI0Y1dkN2pSOHUvSzBmUmVBdmE4ak5LYkpxbTc5QXMx?=
 =?utf-8?B?Nk1lOERuTDhBZXZGenUrZ2hPWHQrVy9scGRTWFFMTTdxaWxNWm05YnhsYTFN?=
 =?utf-8?B?L1BOTWc2Tnk4K3pUS1QycmMvdWZ0dVFCU2JLQkp6M3F2L0tCNWlOaDl4eit3?=
 =?utf-8?B?VitUQ25JRnExbFY0eXJHcTNlTEE4MEpJck9lUkpXb0g0TzhVM2RXTWppUTNP?=
 =?utf-8?B?UUZadXU0RVh1STBwbDdROXcvbkZ2Ukpob2ZVR29VdTdoNElqUFpaMDFCYVdF?=
 =?utf-8?B?WDE5TnI0WUpvbHZmYnpkbGRKcStUL2hkM1llSkFUTXIrUGN3UmhYMVk2ZzRr?=
 =?utf-8?B?Q3AzMUhEKzQyL0dFRXYwbVV3L3MwUWdJSzhtTVVTMmxFZ3p0S2JVK2tmeXYv?=
 =?utf-8?B?bi9abXpjcWs5UFh0Z2c2dDlOTlJ3V1I1Z2NUdGNTVFhqSkdrOXNKTFpFTWtT?=
 =?utf-8?B?VmZETzZGdjRsMTkyb1QyZDh2c0VPSW4xRGFJTEdxL0pJMHpGTEFKUW5uMnpG?=
 =?utf-8?B?SFE9PQ==?=
X-OriginatorOrg: lenbrook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: e75526e7-2994-4a57-44f4-08db27ff869a
X-MS-Exchange-CrossTenant-AuthSource: YT4PR01MB9670.CANPRD01.PROD.OUTLOOK.COM
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2023 22:24:23.2563
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3089fb55-f9f3-4ac8-ba44-52ac0e467cb6
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: f1HQouJl0/clkvMF7u9kdZps4DqhrhEmpYnB2LFPl2q4VnsTKh/DK2hYBl2r/7IfDay3IsF+8Hrh3YL57cU7EtUEsOqsLedQTRIXO2qtb+c=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: YT2PR01MB8807
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

When using gpio based chip select the cs value can go outside the range
0 – 3. The various MX51_ECSPI_* macros did not take this into consideration
resulting in possible corruption of the configuration.

For example for any cs value over 3 the SCLKPHA bits would not be set and
other values in the register possibly corrupted.

One way to fix this is to just mask the cs bits to 2 bits. This still
allows all 4 native chip selects to work as well as gpio chip selects
(which can use any of the 4 chip select configurations).

Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com>
---
 drivers/spi/spi-imx.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index e4ccd0c329d0..c61c7ac4c70c 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -252,6 +252,18 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device
 	return true;
 }
 
+/*
+ * Note the number of natively supported chip selects for MX51 is 4. Some
+ * devices may have less actual SS pins but the register map supports 4. When
+ * using gpio chip selects the cs values passed into the macros below can go
+ * outside the range 0 - 3. We therefore need to limit the cs value to avoid
+ * corrupting bits outside the allocated locations.
+ *
+ * The simplest way to do this is to just mask the cs bits to 2 bits. This
+ * still allows all 4 native chip selects to work as well as gpio chip selects
+ * (which can use any of the 4 chip select configurations).
+ */
+
 #define MX51_ECSPI_CTRL		0x08
 #define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
 #define MX51_ECSPI_CTRL_XCH		(1 <<  2)
@@ -260,16 +272,16 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device
 #define MX51_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)
 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
 #define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
-#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
+#define MX51_ECSPI_CTRL_CS(cs)		((cs & 3) << 18)
 #define MX51_ECSPI_CTRL_BL_OFFSET	20
 #define MX51_ECSPI_CTRL_BL_MASK		(0xfff << 20)
 
 #define MX51_ECSPI_CONFIG	0x0c
-#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
-#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
-#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
-#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
-#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
+#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs & 3) +  0))
+#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs & 3) +  4))
+#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs & 3) +  8))
+#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs & 3) + 12))
+#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs & 3) + 20))
 
 #define MX51_ECSPI_INT		0x10
 #define MX51_ECSPI_INT_TEEN		(1 <<  0)
-- 
2.34.1