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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?mz1v12e9vSUIAJgRy6AsJD8tuPuzeSpyPVKkR37zWwsj3LqqbNOIp2itauX9?= =?us-ascii?Q?IXNyxKoapJkmS80HU6VyGPRfmpF7aVtcOPgu9+lByH2dUUsGrjNs8kynKElL?= =?us-ascii?Q?zxywMVpFUtK5Wlz+7H57vhYmN10tOURD+3d7uLriIizSbjdV3NGlAUGo3VVu?= =?us-ascii?Q?smkUE0EsBT+1t6r93cFFl6joob+rIBSWCKq5zWQNA4fOih783PPNUJfx0aYI?= =?us-ascii?Q?mAwttnY6OC688z+Vzf7AbClCLMBnbFibSDzDu/zrLfSqUa6r6PpDF96gZY5D?= =?us-ascii?Q?8emVf0flLB5McrSW8i36QXzW23uySqKDENaXgYUNuDLEBsP1nIF2QLr+gEKV?= =?us-ascii?Q?xqfsRiT64sd0lQhzoEe0CGsQM8Z2oCrhNpLhlHzdVb2ft9Y8Ek95QuHC5vEW?= =?us-ascii?Q?TZLOh2K5zlR2a+ukVskhVt6NsrKjR9mMjXUAbprGADm3KYZ8+YayxMaMJ6k6?= =?us-ascii?Q?aXzmQ9otxF90RyzN07y4SpnpqR9QIG45E3yQr9k5LE535dl3eyDpYwctl1WK?= =?us-ascii?Q?uDExUiBwbQ2B28nIfNiwj63ervOCuM+0vAzw1qlykr0IhbQoT+Ehu8tvTkBS?= =?us-ascii?Q?Si4ucg8Z+j5N8Y9j524hg3dEMQ/zggSSh8ERK7VILSYgT3Z5SpNXrlEka6aT?= =?us-ascii?Q?PW6jUiHrWNJiHPoE6ZBiRPuJO/F9n4bSeUojVafaEGrAMMI80AwxUVKKFZAp?= =?us-ascii?Q?4vhYE/Sjwr6BFHEnZTLqM7mI5vf+BT9uw0zmY7im1vg8lXtoUUkewt3dpHlq?= =?us-ascii?Q?axeQjnDgELZL54qZ13oqmLHTnJQs0QkOB4ybuJC9A2ZyleAEY12vWVeQizqi?= =?us-ascii?Q?/rAXF9KGKWv5SJRQd9n4C7jgNwxE6g0AVz3L5vdhry+9YqpNf63iWaur6HDu?= =?us-ascii?Q?2Ccs/qAI73puC7yLarTrXRMaOZx8vGQuYlnjqiSzkgs+5WCR818H7o2demJ8?= =?us-ascii?Q?MWbRz5SSzxz08IJl+4rckLokzNAxT8UDDL+0tqoy3KAe9ejO2ywVxTgCXuqb?= =?us-ascii?Q?/XMlP8HQ+BKtWnmqeoaT9tgblX8JgJ7k2orGU66pNYgase9xP2hQ1XO5Z1d4?= =?us-ascii?Q?Kg+dNPANhdY51gIoo2HnHATzNaTxVOdUpPP0r2bLxDHQ+8k6d9BX8lvKjhT8?= =?us-ascii?Q?Q0TwlcejBTkFPoxkFKTGxt0M9jWBNk2kQoWEyygdKqc4IJ2iZfdA3HJykgY+?= =?us-ascii?Q?ZDgkjFwQMmNa4RZ5kgwGjLFv5IzuSlgszYaG5qLxNEWGDiKs5vdVfgIp5JBj?= =?us-ascii?Q?etg5bDFoViS9FO9UoGKw8hxE58uK3MSjOIP+nezkXuSXIgMcy6ECvP1FaSkT?= =?us-ascii?Q?sV4yBOPMawvqy0PdS/EpgC8y4LPUC0787yqcbqiXk46Q4WR+KtQcKQ9h4ERh?= =?us-ascii?Q?6her4VQQ/RgrRe3jXhRxIo/KlRlABnpCT/5s4A03WRqx3KAUYm55suXADtky?= =?us-ascii?Q?r+ONGqlgn6C1pQmOlA0SeLpuxEaEK2GR+JHSWuAJlS8fnRmoSsG+q7mDoYf+?= =?us-ascii?Q?F2CG9hdpbFEVW59sg/YXUmCAjoQ4IElch5mNoieFAzyAFAWQM4Zaewx1J2Ju?= =?us-ascii?Q?JrlVlaGZVNWbfNbbC5w/PU5vt6GRqGXycm7UMStbWaw72B4qgcCDZ+ksqfdT?= =?us-ascii?Q?yw=3D=3D?= X-OriginatorOrg: lenbrook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80534bb4-3cf2-47a0-11ca-08db28013b5f X-MS-Exchange-CrossTenant-AuthSource: YT4PR01MB9670.CANPRD01.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2023 22:36:36.0003 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3089fb55-f9f3-4ac8-ba44-52ac0e467cb6 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fsxz+LmE8xNuPST2xv0Z7VFXiwsTsRxThvycWrUNK8APMaJmGyTo24Rs0iSvba74b0iurV8/N/zCE5r+DTwa18lCdJ40/w455bikzEyGiEI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: YT2PR01MB8856 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In some cases the NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD interrupt flag is not set along with NWL_DSI_RX_PKT_HDR_RCVD when the initial interrupt fires. Since the NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK was not set then the ISR does not fire again when NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD is finally set and the read times out. Also the read packet handling checks for NWL_DSI_DPHY_DIRECTION which is not always set when the ISR for reading the payload runs. Instead it seems better to check xfer->direction is DSI_PACKET_RECEIVE (more similar to the send packet case). The above two changes were required to perform a successful DCS read from a display with a Chipone ICNL9707 driver IC. Signed-off-by: Kevin Groeneveld --- drivers/gpu/drm/bridge/nwl-dsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index 6dc2a4e191d7..241568a17f60 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -334,6 +334,7 @@ static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi) { u32 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK | NWL_DSI_RX_PKT_HDR_RCVD_MASK | + NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK | NWL_DSI_TX_FIFO_OVFLW_MASK | NWL_DSI_HS_TX_TIMEOUT_MASK); @@ -489,7 +490,7 @@ static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status) status & NWL_DSI_TX_PKT_DONE) { xfer->status = xfer->tx_len; end_packet = true; - } else if (status & NWL_DSI_DPHY_DIRECTION && + } else if (xfer->direction == DSI_PACKET_RECEIVE && ((status & (NWL_DSI_RX_PKT_HDR_RCVD | NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) { end_packet = nwl_dsi_read_packet(dsi, status); -- 2.34.1