Message-ID: <87171ab8-9c6d-3978-6d34-4ae922361307@linaro.org>
Date:   Sun, 19 Mar 2023 12:06:13 +0100
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Thunderbird/102.9.0
Subject: Re: [PATCH 11/15] arm64: dts: nuvoton: Add initial ma35d1 device tree
Content-Language: en-US
To:     Jacky Huang <ychuang570808@gmail.com>, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, lee@kernel.org,
        mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de,
        gregkh@linuxfoundation.org, jirislaby@kernel.org
Cc:     devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
        schung@nuvoton.com, Jacky Huang <ychuang3@nuvoton.com>
References: <20230315072902.9298-1-ychuang570808@gmail.com>
 <20230315072902.9298-12-ychuang570808@gmail.com>
 <fb4f60a7-011e-3745-cc40-631247735f2b@linaro.org>
 <c902606e-8a1b-6673-02c7-7beea5477795@gmail.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <c902606e-8a1b-6673-02c7-7beea5477795@gmail.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk

On 18/03/2023 07:07, Jacky Huang wrote:
> 
>>
>>> +		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
>>> +			      IRQ_TYPE_LEVEL_HIGH)>;
>>> +	};
>>> +
>>> +	uart0:serial@40700000 {
>>> +		compatible = "nuvoton,ma35d1-uart";
>>> +		reg = <0x0 0x40700000 0x0 0x100>;
>>> +		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&clk UART0_GATE>;
>>> +		status = "okay";
>> Why? Drop the line... or convert it to disabled. Otherwise, why every
>> SoC has serial0 enabled? Is it used internally?
> 
> 
> uart0 is on all the way since this SoC booting from the MaskROM boot code,
> 
> load arm-trusted-firmware, load bootloader, and finally load linux  kernel.
> 
> uart0 is also the Linux console.

Are you sure? Maybe my board has UART0 disconnected.

Best regards,
Krzysztof