Message-ID: <4e4b6bfd-89b2-e917-6e20-24f3be54606a@gmail.com>
Date:   Sun, 19 Mar 2023 22:16:34 +0800
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Subject: Re: [PATCH 11/15] arm64: dts: nuvoton: Add initial ma35d1 device tree
Content-Language: en-US
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
        p.zabel@pengutronix.de, gregkh@linuxfoundation.org,
        jirislaby@kernel.org
Cc:     devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
        schung@nuvoton.com, Jacky Huang <ychuang3@nuvoton.com>
References: <20230315072902.9298-1-ychuang570808@gmail.com>
 <20230315072902.9298-12-ychuang570808@gmail.com>
 <fb4f60a7-011e-3745-cc40-631247735f2b@linaro.org>
 <c902606e-8a1b-6673-02c7-7beea5477795@gmail.com>
 <87171ab8-9c6d-3978-6d34-4ae922361307@linaro.org>
From:   Jacky Huang <ychuang570808@gmail.com>
In-Reply-To: <87171ab8-9c6d-3978-6d34-4ae922361307@linaro.org>
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Dear Krzyszto,


On 2023/3/19 下午 07:06, Krzysztof Kozlowski wrote:
> On 18/03/2023 07:07, Jacky Huang wrote:
>>>> +		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
>>>> +			      IRQ_TYPE_LEVEL_HIGH)>;
>>>> +	};
>>>> +
>>>> +	uart0:serial@40700000 {
>>>> +		compatible = "nuvoton,ma35d1-uart";
>>>> +		reg = <0x0 0x40700000 0x0 0x100>;
>>>> +		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
>>>> +		clocks = <&clk UART0_GATE>;
>>>> +		status = "okay";
>>> Why? Drop the line... or convert it to disabled. Otherwise, why every
>>> SoC has serial0 enabled? Is it used internally?
>>
>> uart0 is on all the way since this SoC booting from the MaskROM boot code,
>>
>> load arm-trusted-firmware, load bootloader, and finally load linux  kernel.
>>
>> uart0 is also the Linux console.
> Are you sure? Maybe my board has UART0 disconnected.
>
> Best regards,
> Krzysztof


OK, I will have the uart0 disabled in dtsi, and enabled it in dts.


Best regards,

Jacky Huang