Date:   Mon, 20 Mar 2023 05:57:46 +0000
Mime-Version: 1.0
Message-ID: <20230320055746.2070049-1-joychakr@google.com>
Subject: [PATCH] spi: dw: Add 32 bpw support to DW DMA Controller
From:   Joy Chakraborty <joychakr@google.com>
To:     Serge Semin <fancer.lancer@gmail.com>,
        Mark Brown <broonie@kernel.org>
Cc:     linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
        manugautam@google.com, rohitner@google.com,
        Joy Chakraborty <joychakr@google.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

If DW Controller is capable of 32 bits per word support then SW or DMA
controller has to write 32bit or 4byte data to the FIFO at a time.

This Patch adds support for AxSize = 4 bytes configuration from dw dma
driver if n_bytes i.e. number of bytes per write to fifo is 4.

Signed-off-by: Joy Chakraborty <joychakr@google.com>
---
 drivers/spi/spi-dw-dma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index ababb910b391..7d06ecfdebe1 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -212,6 +212,8 @@ static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
 		return DMA_SLAVE_BUSWIDTH_1_BYTE;
 	else if (n_bytes == 2)
 		return DMA_SLAVE_BUSWIDTH_2_BYTES;
+	else if (n_bytes == 4)
+		return DMA_SLAVE_BUSWIDTH_4_BYTES;
 
 	return DMA_SLAVE_BUSWIDTH_UNDEFINED;
 }
-- 
2.40.0.rc1.284.g88254d51c5-goog