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[212.114.21.58]) by smtp.gmail.com with ESMTPSA id c15-20020adffb0f000000b002c6e8cb612fsm8537741wrr.92.2023.03.20.03.44.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Mar 2023 03:44:16 -0700 (PDT) Message-ID: Date: Mon, 20 Mar 2023 11:44:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH] drm/bridge: nwl-dsi: fix packet read ISR handling Content-Language: en-US To: Kevin Groeneveld , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20230318223621.4239-1-kgroeneveld@lenbrook.com> Organization: Linaro Developer Services In-Reply-To: <20230318223621.4239-1-kgroeneveld@lenbrook.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 18/03/2023 23:36, Kevin Groeneveld wrote: > In some cases the NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD interrupt flag is not > set along with NWL_DSI_RX_PKT_HDR_RCVD when the initial interrupt fires. > Since the NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK was not set then the ISR > does not fire again when NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD is finally set > and the read times out. > > Also the read packet handling checks for NWL_DSI_DPHY_DIRECTION which is > not always set when the ISR for reading the payload runs. Instead it seems > better to check xfer->direction is DSI_PACKET_RECEIVE (more similar to the > send packet case). > > The above two changes were required to perform a successful DCS read from > a display with a Chipone ICNL9707 driver IC. > > Signed-off-by: Kevin Groeneveld Thanks for the patch, can you provide a Fixes tag ? Neil > --- > drivers/gpu/drm/bridge/nwl-dsi.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c > index 6dc2a4e191d7..241568a17f60 100644 > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > @@ -334,6 +334,7 @@ static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi) > { > u32 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK | > NWL_DSI_RX_PKT_HDR_RCVD_MASK | > + NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK | > NWL_DSI_TX_FIFO_OVFLW_MASK | > NWL_DSI_HS_TX_TIMEOUT_MASK); > > @@ -489,7 +490,7 @@ static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status) > status & NWL_DSI_TX_PKT_DONE) { > xfer->status = xfer->tx_len; > end_packet = true; > - } else if (status & NWL_DSI_DPHY_DIRECTION && > + } else if (xfer->direction == DSI_PACKET_RECEIVE && > ((status & (NWL_DSI_RX_PKT_HDR_RCVD | > NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) { > end_packet = nwl_dsi_read_packet(dsi, status);