From:   Bartosz Wawrzyniak <bwawrzyn@cisco.com>
To:     vigneshr@ti.com, tjoseph@cadence.com, lpieralisi@kernel.org,
        kw@linux.com, robh@kernel.org, bhelgaas@google.com
Cc:     linux-omap@vger.kernel.org, linux-pci@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        xe-linux-external@cisco.com, danielwa@cisco.com, olicht@cisco.com,
        mawierzb@cisco.com, Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Subject: [PATCH] PCI: cadence: Move 28 bit mask CPU addr fixup ops from platform device to J721E platform
Date:   Mon, 20 Mar 2023 10:41:34 -0700
Message-Id: <20230320174134.3418224-1-bwawrzyn@cisco.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

The 28 bit mask CPU addr fixup is used for generic platform device. However,
not all platforms require to mask 32 bit CPU address. Move 28 bit mask CPU addr
fixup ops to J721E SoC platform driver and use empty as a default one.

28 bit mask was introduced in commit d07701a17aec ("PCI: cadence: Add
new *ops* for CPU addr fixup").

Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
---
 drivers/pci/controller/cadence/pci-j721e.c       |  8 ++++++++
 .../pci/controller/cadence/pcie-cadence-plat.c   | 16 ++++++----------
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 918e11082e6a..9436ae322d58 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -35,6 +35,8 @@
 #define J721E_PCIE_USER_LINKSTATUS	0x14
 #define LINK_STATUS			GENMASK(1, 0)

+#define CDNS_PLAT_CPU_TO_BUS_ADDR	0x0FFFFFFF
+
 enum link_status {
 	NO_RECEIVERS_DETECTED,
 	LINK_TRAINING_IN_PROGRESS,
@@ -156,10 +158,16 @@ static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
 	return false;
 }

+static u64 j721e_pcie_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
+{
+	return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
+}
+
 static const struct cdns_pcie_ops j721e_pcie_ops = {
 	.start_link = j721e_pcie_start_link,
 	.stop_link = j721e_pcie_stop_link,
 	.link_up = j721e_pcie_link_up,
+	.cpu_addr_fixup = j721e_pcie_cpu_addr_fixup,
 };

 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index a224afadbcc0..8b8a072fdd9d 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -13,7 +13,6 @@
 #include <linux/of_device.h>
 #include "pcie-cadence.h"

-#define CDNS_PLAT_CPU_TO_BUS_ADDR	0x0FFFFFFF

 /**
  * struct cdns_plat_pcie - private data for this PCIe platform driver
@@ -30,16 +29,9 @@ struct cdns_plat_pcie_of_data {
 	bool is_rc;
 };

-static const struct of_device_id cdns_plat_pcie_of_match[];
-
-static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
-{
-	return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
-}
+static struct cdns_pcie_ops cdns_plat_ops;

-static const struct cdns_pcie_ops cdns_plat_ops = {
-	.cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
-};
+static const struct of_device_id cdns_plat_pcie_of_match[];

 static int cdns_plat_pcie_probe(struct platform_device *pdev)
 {
@@ -77,6 +69,8 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)

 		rc = pci_host_bridge_priv(bridge);
 		rc->pcie.dev = dev;
+
+		/* Set default bus ops */
 		rc->pcie.ops = &cdns_plat_ops;
 		cdns_plat_pcie->pcie = &rc->pcie;
 		cdns_plat_pcie->is_rc = is_rc;
@@ -105,6 +99,8 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
 			return -ENOMEM;

 		ep->pcie.dev = dev;
+
+		/* Set default bus ops */
 		ep->pcie.ops = &cdns_plat_ops;
 		cdns_plat_pcie->pcie = &ep->pcie;
 		cdns_plat_pcie->is_rc = is_rc;
--
2.35.6