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Mon, 20 Mar 2023 23:30:30 GMT Received: from [10.110.115.97] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 20 Mar 2023 16:30:29 -0700 Message-ID: <394ed3a3-678e-d2bb-a032-aee135acaee2@quicinc.com> Date: Mon, 20 Mar 2023 16:30:29 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v2 5/7] remoteproc: qcom: q6v5: Add support for q6 rmb registers Content-Language: en-US To: Bjorn Andersson CC: Andy Gross , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Mathieu Poirier , Robert Marko , Guru Das Srinagesh , Konrad Dybcio , Manivannan Sadhasivam , , , , References: <20230306231202.12223-1-quic_molvera@quicinc.com> <20230306231202.12223-6-quic_molvera@quicinc.com> <20230316021736.d53quam5eew5fr6m@ripper> From: Melody Olvera In-Reply-To: <20230316021736.d53quam5eew5fr6m@ripper> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rcdnS3O8jz_GPnWPvXR5YtvdQ2TTR5CQ X-Proofpoint-ORIG-GUID: rcdnS3O8jz_GPnWPvXR5YtvdQ2TTR5CQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-20_16,2023-03-20_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303200198 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/15/2023 7:17 PM, Bjorn Andersson wrote: > On Mon, Mar 06, 2023 at 03:12:00PM -0800, Melody Olvera wrote: >> When attaching a running Q6, the remoteproc driver needs a way >> to communicate with the Q6 using rmb registers, so allow the >> rmb register to be gotten from the device tree if present. >> >> Signed-off-by: Melody Olvera >> --- >> drivers/remoteproc/qcom_q6v5.c | 9 +++++++++ >> drivers/remoteproc/qcom_q6v5.h | 8 ++++++++ >> 2 files changed, 17 insertions(+) >> >> diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c >> index 192c7aa0e39e..e8c6be70ebfd 100644 >> --- a/drivers/remoteproc/qcom_q6v5.c >> +++ b/drivers/remoteproc/qcom_q6v5.c >> @@ -254,6 +254,7 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev, >> void (*handover)(struct qcom_q6v5 *q6v5)) >> { >> int ret; >> + struct resource *res; >> >> q6v5->rproc = rproc; >> q6v5->dev = &pdev->dev; >> @@ -263,6 +264,14 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev, >> init_completion(&q6v5->start_done); >> init_completion(&q6v5->stop_done); >> >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > In addition to the PAS driver, __func__ is being invoked by the non-PAS > ADSP and MPSS drivers as well, which both uses reg[1] for other > purposes. So this won't work. > > Perhaps I'm missing some possibility of reuse, but it seems reasonable > for this to move to the pas-driver. Yeah that's fairly sensible. I'll move this to the pas driver. Thanks, Melody > > Thanks, > Bjorn > >> + if (res) { >> + q6v5->rmb_base = devm_ioremap_resource(&pdev->dev, res); >> + if (IS_ERR(q6v5->rmb_base)) >> + q6v5->rmb_base = NULL; >> + } else >> + q6v5->rmb_base = NULL; >> + >> q6v5->wdog_irq = platform_get_irq_byname(pdev, "wdog"); >> if (q6v5->wdog_irq < 0) >> return q6v5->wdog_irq; >> diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h >> index 5a859c41896e..95824d5b64ce 100644 >> --- a/drivers/remoteproc/qcom_q6v5.h >> +++ b/drivers/remoteproc/qcom_q6v5.h >> @@ -7,6 +7,12 @@ >> #include >> #include >> >> +#define RMB_BOOT_WAIT_REG 0x8 >> +#define RMB_BOOT_CONT_REG 0xC >> +#define RMB_Q6_BOOT_STATUS_REG 0x10 >> + >> +#define RMB_POLL_MAX_TIMES 250 >> + >> struct icc_path; >> struct rproc; >> struct qcom_smem_state; >> @@ -16,6 +22,8 @@ struct qcom_q6v5 { >> struct device *dev; >> struct rproc *rproc; >> >> + void __iomem *rmb_base; >> + >> struct qcom_smem_state *state; >> struct qmp *qmp; >> >> -- >> 2.25.1 >>