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In-Reply-To: <20230320212029.3154407-1-david.e.box@linux.intel.com>
From:   Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Date:   Mon, 20 Mar 2023 20:40:47 -0400
Message-ID: <CAE2upjTu98gf9EWKV1X1tP9q7M+vWtniGri+ccgj3BTnh+2QDQ@mail.gmail.com>
Subject: Re: [PATCH] platform/x86/intel/pmc: Alder Lake PCH slp_s0_residency fix
To:     "David E. Box" <david.e.box@linux.intel.com>
Cc:     rajvi.jingar@linux.intel.com, hdegoede@redhat.com,
        markgross@kernel.org, andy.shevchenko@gmail.com,
        linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org
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Looks good to me.  Just a nit, maybe change the subject to "Fix Alder
Lake S0ix reporting" or something like that.

Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>

On Mon, Mar 20, 2023 at 5:20=E2=80=AFPM David E. Box
<david.e.box@linux.intel.com> wrote:
>
> From: Rajvi Jingar <rajvi.jingar@linux.intel.com>
>
> For platforms with Alder Lake PCH (Alder Lake S and Raptor Lake S) the
> slp_s0_residency attribute has been reporting the wrong value. Unlike oth=
er
> platforms, ADL PCH does not have a counter for the time that the SLP_S0
> signal was asserted. Instead, firmware uses the aggregate of the Low Powe=
r
> Mode (LPM) substate counters as the S0ix value.  Since the LPM counters r=
un
> at a different frequency, this lead to misreporting of the S0ix time.
>
> Add a check for Alder Lake PCH and adjust the frequency accordingly when
> display slp_s0_residency.
>
> Fixes: bbab31101f44 ("platform/x86/intel: pmc/core: Add Alderlake support=
 to pmc core driver")
> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/core.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86=
/intel/pmc/core.c
> index e489d2175e42..61ca7c37fb02 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -66,7 +66,18 @@ static inline void pmc_core_reg_write(struct pmc_dev *=
pmcdev, int reg_offset,
>
>  static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u3=
2 value)
>  {
> -       return (u64)value * pmcdev->map->slp_s0_res_counter_step;
> +       /*
> +        * ADL PCH does not have the SLP_S0 counter and LPM Residency cou=
nters are
> +        * used as a workaround which uses 30.5 usec tick. All other clie=
nt
> +        * programs have the legacy SLP_S0 residency counter that is usin=
g the 122
> +        * usec tick.
> +        */
> +       const int lpm_adj_x2 =3D pmcdev->map->lpm_res_counter_step_x2;
> +
> +       if (pmcdev->map =3D=3D &adl_reg_map)
> +               return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
> +       else
> +               return (u64)value * pmcdev->map->slp_s0_res_counter_step;
>  }
>
>  static int set_etr3(struct pmc_dev *pmcdev)
>
> base-commit: 02c464b73645404654359ad21f368a13735e2850
> --
> 2.34.1
>


--=20
Thanks,
Rajneesh