Date:   Tue, 21 Mar 2023 16:42:28 +0530
From:   Jai Luthra <j-luthra@ti.com>
To:     Vaishnav Achath <vaishnav.a@ti.com>
CC:     <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <j-keerthy@ti.com>, <u-kumar1@ti.com>
Subject: Re: [PATCH v3 1/4] arm64: dts: ti: k3-j721e: Add MCSPI nodes
Message-ID: <20230321111228.v4nml7vztoomsiu6@uda0497096>
References: <20230321082827.14274-1-vaishnav.a@ti.com>
 <20230321082827.14274-2-vaishnav.a@ti.com>
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Hi Vaishnav,

Thanks for the series.

On Mar 21, 2023 at 13:58:24 +0530, Vaishnav Achath wrote:
> J721E has 8 MCSPI instances in the main domain and 3 instances
> in the MCU domain. Add the DT nodes for all the 11 instances and
> keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2
> by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out
> externally.
>=20
> Co-developed-by: Keerthy <j-keerthy@ti.com>
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>

Reviewed-by: Jai Luthra <j-luthra@ti.com>

> ---
>=20
> V2->V3:
>  * Update commit message to mention internal MCSPI loopback.
>=20
> V1->V2:=20
>   * Combine main, mcu domain, MCSPI node addition changes
>   to single commit.
>=20
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 88 +++++++++++++++++++
>  .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      | 33 +++++++
>  2 files changed, 121 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/=
dts/ti/k3-j721e-main.dtsi
> index bfa296dce3a3..a90f076776ce 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -2328,4 +2328,92 @@
>  		bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>;
>  		status =3D "disabled";
>  	};
> +
> +	main_spi0: spi@2100000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02100000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 266 1>;
> +		status =3D "disabled";
> +	};
> +
> +	main_spi1: spi@2110000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02110000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 267 1>;
> +		status =3D "disabled";
> +	};
> +
> +	main_spi2: spi@2120000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02120000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 268 1>;
> +		status =3D "disabled";
> +	};
> +
> +	main_spi3: spi@2130000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02130000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 269 1>;
> +		status =3D "disabled";
> +	};
> +
> +	main_spi4: spi@2140000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02140000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 270 1>;
> +		status =3D "disabled";
> +	};
> +
> +	main_spi5: spi@2150000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02150000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 271 1>;
> +		status =3D "disabled";
> +	};
> +
> +	main_spi6: spi@2160000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02160000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 272 1>;
> +		status =3D "disabled";
> +	};
> +
> +	main_spi7: spi@2170000 {
> +		compatible =3D "ti,am654-mcspi","ti,omap4-mcspi";
> +		reg =3D <0x00 0x02170000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 273 1>;
> +		status =3D "disabled";
> +	};
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64=
/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> index 8ac78034d5d6..24e8125db8c4 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> @@ -425,4 +425,37 @@
>  		bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>;
>  		status =3D "disabled";
>  	};
> +
> +	mcu_spi0: spi@40300000 {
> +		compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi";
> +		reg =3D <0x00 0x040300000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 274 0>;
> +		status =3D "disabled";
> +	};
> +
> +	mcu_spi1: spi@40310000 {
> +		compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi";
> +		reg =3D <0x00 0x040310000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 275 0>;
> +		status =3D "disabled";
> +	};
> +
> +	mcu_spi2: spi@40320000 {
> +		compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi";
> +		reg =3D <0x00 0x040320000 0x00 0x400>;
> +		interrupts =3D <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
> +		clocks =3D <&k3_clks 276 0>;
> +		status =3D "disabled";
> +	};
>  };
> --=20
> 2.17.1
>=20
>=20

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