Message-ID: <c087fa09f92838b4e1a2a3e7139b7106.sboyd@kernel.org>
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <20230320204042.980708-3-mmyangfl@gmail.com>
References: <20230320204042.980708-1-mmyangfl@gmail.com> <20230320204042.980708-3-mmyangfl@gmail.com>
Subject: Re: [PATCH v5 2/5] clk: hisilicon: Extract common functions
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     David Yang <mmyangfl@gmail.com>,
        Michael Turquette <mturquette@baylibre.com>,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
To:     David Yang <mmyangfl@gmail.com>
Date:   Tue, 21 Mar 2023 10:34:28 -0700
User-Agent: alot/0.10
Precedence: bulk

Quoting David Yang (2023-03-20 13:40:35)
> To be reused with other Hi3798 series SoCs.
>=20
> Signed-off-by: David Yang <mmyangfl@gmail.com>
> ---

Please squash this patch in

---8<---
diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg=
-hi3798.c
index 3a8d70b7c8ec..0d6886bca3ba 100644
--- a/drivers/clk/hisilicon/crg-hi3798.c
+++ b/drivers/clk/hisilicon/crg-hi3798.c
@@ -203,8 +203,9 @@ struct hi3798_clks {
 	int complex_clks_nums;
 };
=20
-static struct hisi_clock_data *hi3798_clk_register(
-		struct platform_device *pdev, const struct hi3798_clks *clks)
+static struct hisi_clock_data *
+hi3798_clk_register(struct platform_device *pdev,
+		    const struct hi3798_clks *clks)
 {
 	struct hisi_clock_data *clk_data;
 	int ret;
@@ -257,8 +258,8 @@ static struct hisi_clock_data *hi3798_clk_register(
 	return ERR_PTR(ret);
 }
=20
-static void hi3798_clk_unregister(
-		struct platform_device *pdev, const struct hi3798_clks *clks)
+static void hi3798_clk_unregister(struct platform_device *pdev,
+				  const struct hi3798_clks *clks)
 {
 	struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev);
=20
@@ -276,8 +277,9 @@ static void hi3798_clk_unregister(
=20
 #define HI3798_SYSCTRL_NR_CLKS 16
=20
-static struct hisi_clock_data *hi3798_sysctrl_clk_register(
-		struct platform_device *pdev, const struct hi3798_clks *clks)
+static struct hisi_clock_data *
+hi3798_sysctrl_clk_register(struct platform_device *pdev,
+			    const struct hi3798_clks *clks)
 {
 	struct hisi_clock_data *clk_data;
 	int ret;
@@ -302,8 +304,8 @@ static struct hisi_clock_data *hi3798_sysctrl_clk_regis=
ter(
 	return ERR_PTR(ret);
 }
=20
-static void hi3798_sysctrl_clk_unregister(
-		struct platform_device *pdev, const struct hi3798_clks *clks)
+static void hi3798_sysctrl_clk_unregister(struct platform_device *pdev,
+					  const struct hi3798_clks *clks)
 {
 	struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev);
=20
@@ -623,8 +625,8 @@ static const struct hi3798_clks hi3798cv200_crg_clks =
=3D {
 	.phase_clks_nums =3D ARRAY_SIZE(hi3798mv100_phase_clks),
 };
=20
-static struct hisi_clock_data *hi3798cv200_clk_register(
-				struct platform_device *pdev)
+static struct hisi_clock_data *
+hi3798cv200_clk_register(struct platform_device *pdev)
 {
 	return hi3798_clk_register(pdev, &hi3798cv200_crg_clks);
 }
@@ -653,8 +655,8 @@ static const struct hi3798_clks hi3798cv200_sysctrl_clk=
s =3D {
 	.gate_clks_nums =3D ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
 };
=20
-static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
-					struct platform_device *pdev)
+static struct hisi_clock_data *
+hi3798cv200_sysctrl_clk_register(struct platform_device *pdev)
 {
 	return hi3798_sysctrl_clk_register(pdev, &hi3798cv200_sysctrl_clks);
 }


> diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/c=
rg-hi3798.c
> index 7e9507de2..2f8f14e73 100644
> --- a/drivers/clk/hisilicon/crg-hi3798.c
> +++ b/drivers/clk/hisilicon/crg-hi3798.c
> @@ -59,6 +59,119 @@ static const struct hisi_fixed_rate_clock hi3798_fixe=
d_rate_clks[] =3D {
>         { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, },
>  };
> =20
> +struct hi3798_clks {
> +       const struct hisi_gate_clock *gate_clks;
> +       int gate_clks_nums;
> +       const struct hisi_mux_clock *mux_clks;
> +       int mux_clks_nums;
> +       const struct hisi_phase_clock *phase_clks;
> +       int phase_clks_nums;
> +};
> +
> +static struct hisi_clock_data *hi3798_clk_register(
> +               struct platform_device *pdev, const struct hi3798_clks *c=
lks)
> +{
> +       struct hisi_clock_data *clk_data;
> +       int ret;
> +
> +       clk_data =3D hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS);
> +       if (!clk_data)
> +               return ERR_PTR(-ENOMEM);
> +
> +       /* hisi_phase_clock is resource managed */
> +       ret =3D hisi_clk_register_phase(&pdev->dev, clks->phase_clks,
> +                                     clks->phase_clks_nums, clk_data);
> +       if (ret)
> +               return ERR_PTR(ret);
> +
> +       ret =3D hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks,
> +                                          ARRAY_SIZE(hi3798_fixed_rate_c=
lks),
> +                                          clk_data);
> +       if (ret)
> +               return ERR_PTR(ret);
> +
> +       ret =3D hisi_clk_register_mux(clks->mux_clks, clks->mux_clks_nums=
, clk_data);
> +       if (ret)
> +               goto unregister_fixed_rate;
> +
> +       ret =3D hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_n=
ums, clk_data);

Please make a follow-up patch that passes the pdev->dev pointer to these
registration functions so they can use devm APIs.

> +       if (ret)
> +               goto unregister_mux;
> +
> +       ret =3D of_clk_add_provider(pdev->dev.of_node,

Please make a follow-up patch that migrates this to
devm_of_clk_add_hw_provider.

> +                       of_clk_src_onecell_get, &clk_data->clk_data);
> +       if (ret)
> +               goto unregister_gate;
> +