Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8F9FC6FD20 for ; Tue, 21 Mar 2023 20:26:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230155AbjCUU0P convert rfc822-to-8bit (ORCPT ); Tue, 21 Mar 2023 16:26:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229487AbjCUU0N (ORCPT ); Tue, 21 Mar 2023 16:26:13 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2D8D2D64; Tue, 21 Mar 2023 13:26:09 -0700 (PDT) Received: from ip4d1634d3.dynamic.kabel-deutschland.de ([77.22.52.211] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1peiYQ-000417-2m; Tue, 21 Mar 2023 21:25:58 +0100 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Palmer Dabbelt , Evan Green Cc: slewis@rivosinc.com, Conor Dooley , vineetg@rivosinc.com, Evan Green , Conor Dooley , Albert Ou , Andrew Bresticker , Celeste Liu , Guo Ren , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v4 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Tue, 21 Mar 2023 21:25:56 +0100 Message-ID: <22291092.EfDdHjke4D@diego> In-Reply-To: <20230314183220.513101-4-evan@rivosinc.com> References: <20230314183220.513101-1-evan@rivosinc.com> <20230314183220.513101-4-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 14. M?rz 2023, 19:32:17 CET schrieb Evan Green: > We have an implicit set of base behaviors that userspace depends on, > which are mostly defined in various ISA specifications. > > Co-developed-by: Palmer Dabbelt > Signed-off-by: Palmer Dabbelt > Signed-off-by: Evan Green > Reviewed-by: Conor Dooley This needs one fix, described blow, with that applied: Reviewed-by: Heiko Stuebner > + case RISCV_HWPROBE_KEY_IMA_EXT_0: > + pair->value = 0; > + if (has_fpu()) > + pair->value |= RISCV_HWPROBE_IMA_FD; > + > + if (elf_hwcap & RISCV_ISA_EXT_c) This wants to be if (elf_hwcap & riscv_isa_extension_mask(c)) i.e. elf_hwcap is a bitmap, RISCV_ISA_EXT_c is the number "2" and riscv_isa_extension_mask() will get you the shifted bit. > + pair->value |= RISCV_HWPROBE_IMA_C; > + > + break; > > /* > * For forward compatibility, unknown keys don't fail the whole > Heiko