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Message-ID: <0071fdc1-fa53-e096-19c7-ecd1a9d56e86@gmail.com>
Date:   Tue, 21 Mar 2023 16:00:29 -0700
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Subject: Re: [PATCH v3 4/4] clk: bcm: Add BCM63268 timer clock and reset
 driver
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To:     Stephen Boyd <sboyd@kernel.org>, devicetree@vger.kernel.org,
        jonas.gorski@gmail.com, krzysztof.kozlowski+dt@linaro.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        mturquette@baylibre.com, p.zabel@pengutronix.de,
        robh+dt@kernel.org, william.zhang@broadcom.com,
        =?UTF-8?Q?=c3=81lvaro_Fern=c3=a1ndez_Rojas?= <noltari@gmail.com>
References: <20210315122605.28437-1-noltari@gmail.com>
 <20230321201022.1052743-1-noltari@gmail.com>
 <20230321201022.1052743-5-noltari@gmail.com>
 <3a1d7b271a42324c056d983e1943b386.sboyd@kernel.org>
From:   Florian Fainelli <f.fainelli@gmail.com>
In-Reply-To: <3a1d7b271a42324c056d983e1943b386.sboyd@kernel.org>
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On 3/21/23 15:57, Stephen Boyd wrote:
> Quoting Álvaro Fernández Rojas (2023-03-21 13:10:22)
>> diff --git a/drivers/clk/bcm/clk-bcm63268-timer.c b/drivers/clk/bcm/clk-bcm63268-timer.c
>> new file mode 100644
>> index 000000000000..6a1fdd193cb5
>> --- /dev/null
>> +++ b/drivers/clk/bcm/clk-bcm63268-timer.c
>> @@ -0,0 +1,232 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * BCM63268 Timer Clock and Reset Controller Driver
> [...]
>> +
>> +static inline struct bcm63268_tclkrst_hw *
>> +to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
>> +{
>> +       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
>> +}
>> +
>> +static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
>> +                               unsigned long id, bool assert)
>> +{
>> +       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
>> +       unsigned long flags;
>> +       uint32_t val;
>> +
>> +       spin_lock_irqsave(&reset->lock, flags);
>> +       val = __raw_readl(reset->regs);
> 
> Use regular ol readl() here, unless you have some need for no barrires
> or byte swapping.

These SoCs are big-endian, require native endian register access and 
have no posted writes within their bus logic (UBUS) and require no 
barriers, hence the use of __raw_readl() and __raw_writel() is adequate.
-- 
Florian