Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <3a1d7b271a42324c056d983e1943b386.sboyd@kernel.org>
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <20230321201022.1052743-5-noltari@gmail.com>
References: <20210315122605.28437-1-noltari@gmail.com> <20230321201022.1052743-1-noltari@gmail.com> <20230321201022.1052743-5-noltari@gmail.com>
Subject: Re: [PATCH v3 4/4] clk: bcm: Add BCM63268 timer clock and reset driver
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez?= Rojas <noltari@gmail.com>
To:     devicetree@vger.kernel.org, f.fainelli@gmail.com,
        jonas.gorski@gmail.com, krzysztof.kozlowski+dt@linaro.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        mturquette@baylibre.com, p.zabel@pengutronix.de,
        robh+dt@kernel.org, william.zhang@broadcom.com,
        =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez?= Rojas <noltari@gmail.com>
Date:   Tue, 21 Mar 2023 15:57:34 -0700
User-Agent: alot/0.10
Precedence: bulk

Quoting =C3=81lvaro Fern=C3=A1ndez Rojas (2023-03-21 13:10:22)
> diff --git a/drivers/clk/bcm/clk-bcm63268-timer.c b/drivers/clk/bcm/clk-b=
cm63268-timer.c
> new file mode 100644
> index 000000000000..6a1fdd193cb5
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-bcm63268-timer.c
> @@ -0,0 +1,232 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * BCM63268 Timer Clock and Reset Controller Driver
[...]
> +
> +static inline struct bcm63268_tclkrst_hw *
> +to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
> +{
> +       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
> +}
> +
> +static int bcm63268_timer_reset_update(struct reset_controller_dev *rcde=
v,
> +                               unsigned long id, bool assert)
> +{
> +       struct bcm63268_tclkrst_hw *reset =3D to_bcm63268_timer_reset(rcd=
ev);
> +       unsigned long flags;
> +       uint32_t val;
> +
> +       spin_lock_irqsave(&reset->lock, flags);
> +       val =3D __raw_readl(reset->regs);

Use regular ol readl() here, unless you have some need for no barrires
or byte swapping.

> +       if (assert)
> +               val &=3D ~BIT(id);
> +       else
> +               val |=3D BIT(id);
> +       __raw_writel(val, reset->regs);

Same.

> +       spin_unlock_irqrestore(&reset->lock, flags);
> +
> +       return 0;
> +}
> +
[...]
> +
> +static int bcm63268_tclk_probe(struct platform_device *pdev)
> +{
> +       struct device *dev =3D &pdev->dev;
> +       const struct bcm63268_tclk_table_entry *entry, *table;
> +       struct bcm63268_tclkrst_hw *hw;
> +       struct clk_hw *clk;
> +       u8 maxbit =3D 0;
> +       int i, ret;
> +
> +       table =3D of_device_get_match_data(dev);

Use device_get_match_data() instead.

> +       if (!table)
> +               return -EINVAL;
> +
> +       for (entry =3D table; entry->name; entry++)
> +               maxbit =3D max(maxbit, entry->bit);
> +       maxbit++;
> +
> +       hw =3D devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
> +                         GFP_KERNEL);
> +       if (!hw)
> +               return -ENOMEM;
> +
> +       platform_set_drvdata(pdev, hw);
> +
> +       spin_lock_init(&hw->lock);
> +
> +       hw->data.num =3D maxbit;
> +       for (i =3D 0; i < maxbit; i++)
> +               hw->data.hws[i] =3D ERR_PTR(-ENODEV);
> +
> +       hw->regs =3D devm_platform_ioremap_resource(pdev, 0);
> +       if (IS_ERR(hw->regs))
> +               return PTR_ERR(hw->regs);
> +
> +       for (entry =3D table; entry->name; entry++) {
> +               clk =3D clk_hw_register_gate(dev, entry->name, NULL, 0,

Use devm?

> +                                          hw->regs, entry->bit,
> +                                          CLK_GATE_BIG_ENDIAN, &hw->lock=
);
> +               if (IS_ERR(clk)) {
> +                       ret =3D PTR_ERR(clk);
> +                       goto out_err;
> +               }
> +
> +               hw->data.hws[entry->bit] =3D clk;
> +       }
> +
> +       ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> +                                         &hw->data);
> +       if (ret)
> +               return ret;
> +
> +       hw->rcdev.of_node =3D dev->of_node;
> +       hw->rcdev.ops =3D &bcm63268_timer_reset_ops;
> +
> +       ret =3D devm_reset_controller_register(dev, &hw->rcdev);
> +       if (ret)
> +               dev_err(dev, "Failed to register reset controller\n");
> +
> +       return 0;
> +
> +out_err:
> +       for (i =3D 0; i < hw->data.num; i++) {
> +               if (!IS_ERR(hw->data.hws[i]))
> +                       clk_hw_unregister_gate(hw->data.hws[i]);

And then drop this?

> +       }
> +
> +       return ret;
> +}
> +
> +static const struct of_device_id bcm63268_tclk_dt_ids[] =3D {
> +       {
> +               .compatible =3D "brcm,bcm63268-timer-clocks",
> +               .data =3D &bcm63268_timer_clocks,

Are you planning on adding more SoCs to this driver? The data can
currently be always assumed to be bcm63268_timer_clocks

> +       }, {
> +               /* sentinel */
> +       }
> +};
> +