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Subject: Re: [PATCH v3 4/4] clk: bcm: Add BCM63268 timer clock and reset driver
From:   Stephen Boyd <sboyd@kernel.org>
To:     Florian Fainelli <f.fainelli@gmail.com>,
        devicetree@vger.kernel.org, jonas.gorski@gmail.com,
        krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, mturquette@baylibre.com,
        p.zabel@pengutronix.de, robh+dt@kernel.org,
        william.zhang@broadcom.com,
        =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez?= Rojas <noltari@gmail.com>
Date:   Tue, 21 Mar 2023 16:23:51 -0700
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Quoting Florian Fainelli (2023-03-21 16:09:54)
> On 3/21/23 16:06, Stephen Boyd wrote:
> > Quoting Florian Fainelli (2023-03-21 16:00:29)
> >>
> >> These SoCs are big-endian, require native endian register access and
> >> have no posted writes within their bus logic (UBUS) and require no
> >> barriers, hence the use of __raw_readl() and __raw_writel() is adequat=
e.
> >>
> >=20
> > Use ioread32be() then?
>=20
> BCM63xx drivers tend to use __raw_{read,write}l for consistency and to=20
> make it clear that no barriers, no endian swapping is necessary, I would =

> prefer to remain consistent with that convention.

Ok.

Is the clk device big-endian? Or the CPU is big-endian? SoC being
big-endian sounds like the devices in the SoC are big-endian. I hope we
never plop this device down with a CPU that's litle-endian.