Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <db870e74-9d97-740a-9829-5fafc0bb0559@nvidia.com>
Date:   Wed, 22 Mar 2023 11:07:15 +0000
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Thunderbird/102.8.0
Subject: Re: [PATCH v3] i2c: tegra: Share same DMA channel for RX and TX
Content-Language: en-US
To:     Akhil R <akhilrajeev@nvidia.com>, christian.koenig@amd.com,
        digetx@gmail.com, ldewangan@nvidia.com, linux-i2c@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
        sumit.semwal@linaro.org, thierry.reding@gmail.com, wsa@kernel.org
References: <20230322102413.52886-1-akhilrajeev@nvidia.com>
From:   Jon Hunter <jonathanh@nvidia.com>
In-Reply-To: <20230322102413.52886-1-akhilrajeev@nvidia.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?U3ZXYWtJM2FWUnpid05IbHJjckxQYzN5SzZVeFo4c1dEdUNPa0hvK3REMmN0?=
 =?utf-8?B?bFdIQ0hxMjVjLzZJSzllYzdnZ1J5UUVPVXBuUGVkMGF4eWJ4N0FaanNiUHdm?=
 =?utf-8?B?MThtYWhvUmsveXJ2R1A4WUU2NHJYRWZ1Qnp3eFZ6NDl4Z0lvYnBtN0ltMUw3?=
 =?utf-8?B?dmpCNzFXNHlXd3ErMzRjQmRoK2Znd1JCaGNLZkdWc0ttcTkzbXY2ME0rT3Bn?=
 =?utf-8?B?NUszRXZFcUlobFhUbFF3RFdtWlhHNzd5SkNUK01zTElzR3FxMjV1UlNIR0I3?=
 =?utf-8?B?Zmh6K096WkRCWGx2aVNaeVFsak5tQlE5NjBFbDdEV1lzQmxYSlpqSS9hM3lm?=
 =?utf-8?B?aC9nbWxJZTU5WEsrdEN3NFVpZlVkaDhxMjVBamJ1STQ5R0tNamphY2twdVRB?=
 =?utf-8?B?MUZvVWE2V0QxUGNCeXRLdDE2R2hJVThqVmc0VUdxK3JSb3dlYTgzZVZoOTlv?=
 =?utf-8?B?cEVWMUpMZUowcUtMci8xazVZTmtUSWFqZHU4L1pMTWtPYU9QQjdxVm5NbFVX?=
 =?utf-8?B?QmY1TE5TOFk4VEpZcWFSajFEM1diTjcrcDkzZ1pJY1VzVk9KMlpWT2Nyc25s?=
 =?utf-8?B?MFJTRlUyMEJCRlViV0Jud1NHVEl6eTRzMkE0QkFNNzVSVHY0bHdiM2xKOGYv?=
 =?utf-8?B?Y1IzV1hubHlNbWNWd1NMblpMVnpZT2RBTWZ6bU9zTFZXR3dnRnlERllvNkxq?=
 =?utf-8?B?aFpUdFF3a0xWamNVTEdudzhFcmxaa0VpckNRYWVvY2JOZkhSSlJ6WVFhWURh?=
 =?utf-8?B?YlAwTnByMGtVS1ByMEF0MnUxcTRVWmxoTlZTREdpUHcxSXhTMW9VanFhV3BG?=
 =?utf-8?B?bzd3VStMSUk1MWt5Y0V4VENkZm1UM2xvdnAzTURxY0VqMUJiUHpjR2p4WnRz?=
 =?utf-8?B?all6STlCT2xRdUMvY3NRRjE5VnBDeTErNXJCdlRxRndHVVNSeFlIZjE3NThQ?=
 =?utf-8?B?cHhwV3M1VU1TamdYMDBqWWtwcG9RUm1qNlRnSjRiUXpaaVFEL094SVRWR3c3?=
 =?utf-8?B?UTl1d1piOG9tbWtHZG5iQUdnanlyOXEwNm1ZVzhZZEJXMXZMWXZZUDlhZUQ1?=
 =?utf-8?B?M2huKzFhR3Vwa1JEV3NZY2pPaDJ3RHdxM0FPRFZtRE9UQVlTUWxwK0dIQ3kx?=
 =?utf-8?B?UXI1M2UvSERBOExBQW4xZkNSWC9sbXlNT2ZzNEFDTzVtWFdSQ2UwSmlvS0Fp?=
 =?utf-8?B?UjZzc1FUT3BjakptRmpVWWJIYTBWUWNsOEVtUk9PdFlINWZFblNDUUZIZGdm?=
 =?utf-8?B?NHpUZFRqa2JnTzU2QmNzMldVd3lzNXFIRSs4UFJsRnFveFhUbllYcWYwcTcx?=
 =?utf-8?B?S0FLODk2OUg2MDdFNlpJazVOVlNjRFBEbGViR1dwVnFJajFhRVlKNWNUNGEr?=
 =?utf-8?B?UjhxYzdJOURnOFhIQnRVYXNJdnRieGNLdmhCb2FsVENHOVFVYlZzZ3VTTDNY?=
 =?utf-8?B?VXVLRVAzaUpSNzFmZmhDbHQyeE9XWEJVcjZWYkNNVXQzU21NaU95QXlQdGdm?=
 =?utf-8?B?Q2Q1MEJkRUlNZkNuLzdDM0tyZDhOYTNxamVnbVNOVDNtSERKcWpPS2twYVAr?=
 =?utf-8?B?RGJHc1dvU0JNeGZxM3lRb3IwZWMvcUxCbzUvcjRSd0pUS0dMaWtqdnpGUlpP?=
 =?utf-8?B?Q3cyUnk1Qit1WUU1K2JmYnYvT1V3Q2hpcExJdlFLNUtjejdBOE9ZS1Z1a0JJ?=
 =?utf-8?B?SlFOTisyaExjclRCRExpTzZ4ZGxoU3ZCY0l3MUpuWXdua1krcG02VEU4Wm9L?=
 =?utf-8?B?eWZlRUJFYUlNOEFpa1ByRmw2WHQyU1JhelBjOVI5cjhYRzMxU0tWS0N2T3hJ?=
 =?utf-8?B?ZVNtSU9TRDhiOFhGb3VFL2Y4eHlNVFpEaUwxTVZGZmJzN3Nib3VxQncyR3Ja?=
 =?utf-8?B?VXYrWDdOblRIMUZla2VkTlFERVlQUGt4VnI4QUE0SllXbStrNjhsN3RNU1hn?=
 =?utf-8?B?Y2hPSzkxRExGZHg4blBEdjB6TmVnWmsxNUszbWNXbkpJY1VGR0dxb25KSno2?=
 =?utf-8?B?YWNjM1J3VEl1NzNSMUF5MEZEUitOWmR3OEdQUHFvQVhyc3E2ZURSRThUSUpt?=
 =?utf-8?B?aGNzY1dHb0I4VGJMMkt3NDhvWno4c1VEYWlFSUVXeGNNaGJLZzZ6VEx2bDRT?=
 =?utf-8?B?ZkxkMW9LbGVvaklhUnFSRHladzNnQk5XNU9nZTg1MzlYNjcreDRsaGwvV0M4?=
 =?utf-8?B?UW44Nm5LT01CZndxK0k2Y0NUa2trd1NlL1NtVW9WVUdLODJMN1BVb3d3WklE?=
 =?utf-8?B?ZFdIVW41MlNLSHArc1dCQk53Y0FnPT0=?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: c548b475-cc08-427e-9445-08db2ac59ceb
X-MS-Exchange-CrossTenant-AuthSource: CO6PR12MB5444.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2023 11:07:23.5789
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: Fl5stidFamiQXchXz7DfxBv+K7eVSsclQsrQnq2TNkaXJp3dh7W9QeHyZ2r3RZqfQztkcynCMF9Bj4fr9e8pzA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7296
X-Spam-Status: No, score=2.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,NICE_REPLY_A,
        RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SORTED_RECIPS,SPF_HELO_PASS,
        SPF_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6
X-Spam-Level: **
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 22/03/2023 10:24, Akhil R wrote:
> Allocate only one DMA channel for I2C and share it for both TX and RX
> instead of using two different DMA hardware channels with the same
> slave ID. Since I2C supports only half duplex, there is no impact on
> perf with this.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>

Just to confirm. This impacts all Tegra devices from Tegra20 to the 
latest. Does this work for all Tegra and the different DMA controllers 
that they have?

Thanks
Jon

-- 
nvpublic