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From:   =?UTF-8?B?w4FsdmFybyBGZXJuw6FuZGV6IFJvamFz?= <noltari@gmail.com>
Date:   Wed, 22 Mar 2023 18:18:27 +0100
Message-ID: <CAKR-sGfzV0MXY_qGZCepZxXc3uWzWYb3v9fsJdAhoqOA6ikiTw@mail.gmail.com>
Subject: Re: [PATCH v3 0/4] clk: add BCM63268 timer clock and reset
To:     Stephen Boyd <sboyd@kernel.org>
Cc:     devicetree@vger.kernel.org, f.fainelli@gmail.com,
        jonas.gorski@gmail.com, krzysztof.kozlowski+dt@linaro.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        mturquette@baylibre.com, p.zabel@pengutronix.de,
        robh+dt@kernel.org, william.zhang@broadcom.com
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El mar, 21 mar 2023 a las 23:54, Stephen Boyd (<sboyd@kernel.org>) escribi=
=C3=B3:
>
> Quoting =C3=81lvaro Fern=C3=A1ndez Rojas (2023-03-21 13:10:18)
> > Broadcom BCM63268 has a timer clock and reset controller which has the
> > following layout:
> >   #define POR_RESET_STATUS            (1 << 31)
> >   #define HW_RESET_STATUS             (1 << 30)
> >   #define SW_RESET_STATUS             (1 << 29)
> >   #define USB_REF_CLKEN               (1 << 18)
> >   #define UTO_EXTIN_CLKEN             (1 << 17)
> >   #define UTO_CLK50_SEL               (1 << 16)
> >   #define FAP2_PLL_CLKEN              (1 << 15)
> >   #define FAP2_PLL_FREQ_SHIFT         12
> >   #define FAP1_PLL_CLKEN              (1 << 11)
> >   #define FAP1_PLL_FREQ_SHIFT         8
> >   #define WAKEON_DSL                  (1 << 7)
> >   #define WAKEON_EPHY                 (1 << 6)
> >   #define DSL_ENERGY_DETECT_ENABLE    (1 << 4)
> >   #define GPHY_1_ENERGY_DETECT_ENABLE (1 << 3)
> >   #define EPHY_3_ENERGY_DETECT_ENABLE (1 << 2)
> >   #define EPHY_2_ENERGY_DETECT_ENABLE (1 << 1)
> >   #define EPHY_1_ENERGY_DETECT_ENABLE (1 << 0)
> >
> > Also excuse me for the delay in the v3, but I totally forgot about this=
...
>
> Please don't send as a reply to a previous round. It makes applying the
> patch series more difficult and buries the new series deep down in the
> mail thread.

Excuse me for that, but other kernel maintainers prefer it this way.

--
=C3=81lvaro