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Date:   Thu, 23 Mar 2023 09:03:23 +0000
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Conor Dooley <conor@kernel.org>, <hal.feng@starfivetech.com>
CC:     Hal Feng <hal.feng@starfivetech.com>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Ben Dooks <ben.dooks@sifive.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive
 JH7110 device tree
Message-ID: <6ce5b897-f1c2-4b58-9353-9d9e881ad237@spud>
References: <20230320103750.60295-1-hal.feng@starfivetech.com>
 <20230320103750.60295-20-hal.feng@starfivetech.com>
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On Wed, Mar 22, 2023 at 10:02:40PM +0000, Conor Dooley wrote:
> On Mon, Mar 20, 2023 at 06:37:48PM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >=20
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >=20
> > Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
>=20
> > +		S7_0: cpu@0 {
> > +			compatible =3D "sifive,s7", "riscv";
> > +			reg =3D <0>;
> > +			d-cache-block-size =3D <64>;
> > +			d-cache-sets =3D <64>;
> > +			d-cache-size =3D <8192>;
> > +			d-tlb-sets =3D <1>;
> > +			d-tlb-size =3D <40>;
> > +			device_type =3D "cpu";
> > +			i-cache-block-size =3D <64>;
> > +			i-cache-sets =3D <64>;
> > +			i-cache-size =3D <16384>;
> > +			i-tlb-sets =3D <1>;
> > +			i-tlb-size =3D <40>;
> > +			mmu-type =3D "riscv,sv39";
> > +			next-level-cache =3D <&ccache>;
> > +			riscv,isa =3D "rv64imac_zba_zbb";
> > +			tlb-split;
> > +			status =3D "disabled";
>=20
> Jess pointed out on IRC that this S7 entry looks wrong as it is claiming
> that the S7 has an mmu. I didn't go looking back in the history of
> u74-mc core complex manuals, but the latest version does not show an mmu
> for the S7.

BTW Hal, if the dt-binding stuff is okay with Emil, I can just remove
the mmu here if you confirm it is a mistake rather than you needing to
resubmit to remove it.

Cheers,
Conor.

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