Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
To:     airlied@gmail.com
Cc:     daniel@ffwll.ch, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, wenst@chromium.org,
        steven.price@arm.com, alyssa.rosenzweig@collabora.com,
        robh@kernel.org, dri-devel@lists.freedesktop.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        kernel@collabora.com,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 RESEND 0/2] Panfrost: GPU Speed-binning support via OPP
Date:   Thu, 23 Mar 2023 10:08:20 +0100
Message-Id: <20230323090822.61766-1-angelogioacchino.delregno@collabora.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

The OPP framework supports binning through the 'opp-supported-hw'
devicetree property and some of the SoCs that are using Panfrost,
namely ... MediaTek, are actually binned.
This is especially seen in MT8186, but some other models do actually
support the same.

This series adds basic binning support by simply checking (and reading)
speed-bin from NVMEM (eFuse arrays, usually) and *if and only if* that
is provided, adds the read value with devm_pm_opp_set_supported_hw().

This code expects to receive a value that is compatible with how the
supported_hw checks work in OPP and it should never contain any kind
of platform (or SoC) specific code, since Panfrost is a driver for a
GPU that may be tied to different SoCs... and this is what this series
provides.

Cheers!

AngeloGioacchino Del Regno (2):
  dt-bindings: gpu: mali-bifrost: Document nvmem for speedbin support
  drm/panfrost: Add basic support for speed binning

 .../bindings/gpu/arm,mali-bifrost.yaml        |  7 +++++
 drivers/gpu/drm/panfrost/panfrost_devfreq.c   | 30 +++++++++++++++++++
 2 files changed, 37 insertions(+)

-- 
2.40.0