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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Thu, 23 Mar 2023 12:42:02 +0200
Message-ID: <CAHp75VfRr_O2=vr4-5dG0nUpkCXPHtxD2z7tP-ryMM8N+RNv_g@mail.gmail.com>
Subject: Re: [PATCH v12 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support
To:     Brad Larson <blarson@amd.com>
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org,
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On Thu, Mar 23, 2023 at 2:10=E2=80=AFAM Brad Larson <blarson@amd.com> wrote=
:
>
> Add support for AMD Pensando Elba SoC which explicitly
> controls byte-lane enables on writes.
>
> Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which
> allows Elba SoC sdhci_elba_ops to overwrite the SDHCI
> IO memory accessors


> +/* Elba control register bits [6:3] are byte-lane enables */
> +#define ELBA_BYTE_ENABLE_MASK(x)       ((x) << 3)


> +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val,
> +                            void __iomem *reg)
> +{
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&priv->wrlock, flags);
> +       writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);

GENMASK(3, 0) ?

> +       writel(val, reg);
> +       spin_unlock_irqrestore(&priv->wrlock, flags);
> +}

...

> +       byte_enables =3D GENMASK(1, 0) << (reg & 0x3);

   unsigned u32 shift =3D reg & GENMASK(1, 0);

   byte_enables =3D GENMASK(1, 0) << shift;

?

...

> +       byte_enables =3D BIT(0) << (reg & 0x3);

In a similar way?

   unsigned u32 shift =3D reg & GENMASK(1, 0);

   byte_enables =3D BIT(0) << shift;

--=20
With Best Regards,
Andy Shevchenko