Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Thu, 23 Mar 2023 09:17:46 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Nicolin Chen <nicolinc@nvidia.com>
Cc:     Robin Murphy <robin.murphy@arm.com>, will@kernel.org,
        eric.auger@redhat.com, kevin.tian@intel.com,
        baolu.lu@linux.intel.com, joro@8bytes.org,
        shameerali.kolothum.thodi@huawei.com, jean-philippe@linaro.org,
        linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 14/14] iommu/arm-smmu-v3: Add
 arm_smmu_cache_invalidate_user
Message-ID: <ZBxDavy99vg8OA9a@nvidia.com>
References: <ZAtYphmOuEqQ1BiC@nvidia.com>
 <ZAxsgjuuG3ziqs9E@Asurada-Nvidia>
 <ZBhZiCOQHAxEaamy@nvidia.com>
 <ZBiCEAqP1OU5EvoG@Asurada-Nvidia>
 <ZBiEE+QLjPpxBjkQ@nvidia.com>
 <ZBiRAVROma5/Os2S@Asurada-Nvidia>
 <ZBip4sbxUQo8RjGv@nvidia.com>
 <ZBjOooJZcUf182ES@Asurada-Nvidia>
 <ZBjb9sKkAddFmtOU@nvidia.com>
 <ZBtrs3UHK55UUNYe@Asurada-Nvidia>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <ZBtrs3UHK55UUNYe@Asurada-Nvidia>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?yE+s3mXVw+qd3pazXRQucx6XwtSs8hg/aXnJgVoboprfguXrwLEpqGdrovGt?=
 =?us-ascii?Q?1hrOx4kU263vbdgSIJJUUi7/bXwh8G+UsVGMtGGfktqbXwcKfHRAsUvO1USK?=
 =?us-ascii?Q?h5NFPRAsyDOQgU4XwIgnsN62QgwxT9wq1rSe2wBRHB10FihdTrLfYyS1cUoy?=
 =?us-ascii?Q?cUrpFrPzY5PmHsetp0WOktOU0R+WgHT52bc/Th6UW85Wnwamx2nnNTdcFiNe?=
 =?us-ascii?Q?P8Ys91396FuLs54/tXLn6w+2DeoWuldTQ/YatWuZ4+2WZKjdd986aX+ifeUE?=
 =?us-ascii?Q?SSB2SakoDazq/gb5ab5+qXbEy7Xa7lWLp3JBxRwOvwzK6qfMzyEC6QbaUrL4?=
 =?us-ascii?Q?bHtgCWqhdEkQJTHvGvQQET0yDeH1uLdKMOlkYtwQDiVF6WQcNJD4aSnbB/Q9?=
 =?us-ascii?Q?sZNUdUHAIuoIQnj5Or1Ld0hGcWxO8SWtJL+9BZaQq7l8yCnBlVHNbgs37Uo6?=
 =?us-ascii?Q?ECQ2GJLiaqxtYuEyK/OIUXap1zRoPXLDu+X38RtItWhr4s5wDprUARg4Zx17?=
 =?us-ascii?Q?qZ9SyReNtZE5gR/55kpA67jLZSrPHPgscmWlNukarcfjE2vGzkRxGECjtqO4?=
 =?us-ascii?Q?gB8McMUZpNJvqDqqDwgpN0uJBsJHPIyTxQlG0jO4WCXRDHfhRp08PcmZOFbU?=
 =?us-ascii?Q?mE5uf5Idlo8ydat+y+49NRkxX+iURGN89nAXk515dme0Lq0cOl3IwpghFkyL?=
 =?us-ascii?Q?RnKPYINlpaB8JILdIzF7hGgM5bQQw3hRQ1Xx6HpJpOhlSms0Cdxqldf+eGwD?=
 =?us-ascii?Q?K/S+MMAh0kb5c2VFfsRwQc2mD9LL5RtTjMTs4bop7+eRQgd6XpteWYxECPUP?=
 =?us-ascii?Q?Vkm8018pd9MiwlfTE/rksqG5pJjgc7bqPC71Sh4V3K9CJ2WUR4YzDfTMGEzm?=
 =?us-ascii?Q?M7xu/8UvZs+z5SfjJiFFhP7cbhaWdLb10IvXj0kO/r6zpsc6ex+RWXKNviY3?=
 =?us-ascii?Q?G3P+L1ZCaXICYra0R4AJNHtUxgQULdHNAgL2lPhLGpYq+tjX/H96pJpz8viO?=
 =?us-ascii?Q?motjoPjQp92finJMJFzPfpPcOFr/1OdiG/cfDIUaRpRYxvzBp6QYSV45kT2V?=
 =?us-ascii?Q?JmWfN0t2U2+Wcn/YkoU9vlw6iUqKdH19k1JPd+9S2X6vw4VrA5OFUPE8ePXH?=
 =?us-ascii?Q?QwU+uR1qFatfZpgh7tgB1gqiTN2QY7YLXdLIbf6PYOjP09TodVvi9TuxkXJ5?=
 =?us-ascii?Q?Ckw0GnpMu3VZnxKPq/rFTLrUfikiSkqSXPKPs9IFWPbEUc5aOA0Iu1roCeNx?=
 =?us-ascii?Q?cuRcEbWJodJfvvCNJ22hwyYYFIBqx5i16jeiCnXUySPpny+6KKhYEfZANw+o?=
 =?us-ascii?Q?BoJpxb7ZTyeWZb4OLzTVx93Qcm7eSfRnTu8SF1Imbo+AIfX6mTqpEuKIjPO7?=
 =?us-ascii?Q?2kHmqj7KsHp/Sm46z+kpF1wYlM0qb8j5lDP3OspCdzsN0wJ/nlQW38XOi46j?=
 =?us-ascii?Q?vRucJiIoSc5kCPjKoYVPLmpkYUsRBFpmEY1nsYpyA6ilfvFCpcTzrMhNmOUn?=
 =?us-ascii?Q?Mk8/4Ep/InwMm/mAVABcJGqROtzeFG/FsDGoIB7OwkCsGuFlwdLieUYV+zYN?=
 =?us-ascii?Q?FBK66DAS0Ra+ZsdeYJJmq+jHP7M0ia4dlnVjnviV?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 1e29274f-b187-4b1d-c796-08db2b989e3f
X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 12:17:49.4622
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: rDiIwDHrnH4W4NO3JuVux3qP4jWh/rk7K9GDQKoOlyPBDrSvPpn7MhpgpAZHbeRW
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8524
X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,
        RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE
        autolearn=unavailable autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Wed, Mar 22, 2023 at 01:57:23PM -0700, Nicolin Chen wrote:
> On Mon, Mar 20, 2023 at 07:19:34PM -0300, Jason Gunthorpe wrote:
> 
> > > IIUIC, the ioctl for the link of vSID/dev_id should happen at
> > > the stage when boot boots, while the HWPT alloc ioctl happens
> > > at CFGI_STE.
> > 
> > Yes
> >  
> > > > > What could be a good prototype of the ioctl? Would it be a VFIO
> > > > > device one or IOMMUFD one?
> > > > 
> > > > If we load the vSID table it should be a iommufd one, linked to the
> > > > ARM SMMUv3 driver and probably take in a pointer to an array of
> > > > vSID/dev_id pairs. Maybe an add/remove type of operation.
> > > 
> > > Will try some solution.
> > 
> > It is only necessary if you want to do batching
> > 
> > For non-batching the SID invalidation should be done differently with
> > a device_id input instead. That is a bit tricky to organize as you
> > want iommufd to get back a 'struct device *' from the ID.
> 
> I am wondering whether we need to have dev_id, i.e. IOMMUFD,
> in play with the link of pSID<->vSID, as I am thinking of a
> simplified approach by passing the vSID via the hwpt alloc
> structure when we allocate an S2 domain.

No, that doesn't make sense. the vSID is per-STE, the S2 domain is
fully shared. You can't put SID information in the iommu_domains.

JAson