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[46.135.89.179]) by smtp.gmail.com with ESMTPSA id ml23-20020a170906cc1700b0092ce8344078sm8956676ejb.33.2023.03.23.10.24.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:24:04 -0700 (PDT) Date: Thu, 23 Mar 2023 18:24:03 +0100 From: Andrew Jones To: Song Shuai Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor.dooley@microchip.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V2] riscv: export cpu/freq invariant to scheduler Message-ID: <20230323172403.nfrtgm5vea4qvinu@orel> References: <20230323123924.3032174-1-suagrfillet@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230323123924.3032174-1-suagrfillet@gmail.com> X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 23, 2023 at 08:39:24PM +0800, Song Shuai wrote: > RISC-V now manages CPU topology using arch_topology which provides > CPU capacity and frequency related interfaces to access the cpu/freq > invariant in possible heterogeneous or DVFS-enabled platforms. > > Here adds topology.h file to export the arch_topology interfaces for > replacing the scheduler's constant-based cpu/freq invariant accounting. > > Signed-off-by: Song Shuai > --- > changes from V1: > - fix the leading underscore and tidy the patch up > --- > arch/riscv/include/asm/topology.h | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 arch/riscv/include/asm/topology.h > > diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/topology.h > new file mode 100644 > index 000000000000..727e8d163a3b > --- /dev/null > +++ b/arch/riscv/include/asm/topology.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _ASM_RISCV_TOPOLOGY_H > +#define _ASM_RISCV_TOPOLOGY_H > + > +#include > + > +/* Replace task scheduler's default frequency-invariant accounting */ > +#define arch_scale_freq_tick topology_scale_freq_tick > +#define arch_set_freq_scale topology_set_freq_scale I was thinking all the right hand side would line up, which means the above two need additional tabs and so does topology_get_cpu_scale. > +#define arch_scale_freq_capacity topology_get_freq_scale > +#define arch_scale_freq_invariant topology_scale_freq_invariant > + > +/* Replace task scheduler's default cpu-invariant accounting */ > +#define arch_scale_cpu_capacity topology_get_cpu_scale > + > +/* Enable topology flag updates */ > +#define arch_update_cpu_topology topology_update_cpu_topology > + > +#include I'd also prefer a blank line here. > +#endif /* _ASM_RISCV_TOPOLOGY_H */ > -- > 2.20.1 > Otherwise, Reviewed-by: Andrew Jones Thanks, drew