Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Thu, 23 Mar 2023 18:07:26 -0700
From:   Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To:     Dave Hansen <dave.hansen@intel.com>
Cc:     x86@kernel.org, Ricardo Neri <ricardo.neri@intel.com>,
        linux-kernel@vger.kernel.org,
        Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
        Len Brown <len.brown@intel.com>,
        "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
        Zhang Rui <rui.zhang@intel.com>, Chen Yu <yu.c.chen@intel.com>,
        stable@vger.kernel.org
Subject: Re: [PATCH] x86/cacheinfo: Define per-CPU num_cache_leaves
Message-ID: <20230324010726.GA7459@ranerica-svr.sc.intel.com>
References: <20230314231658.30169-1-ricardo.neri-calderon@linux.intel.com>
 <2b1b5ded-522f-1fcf-6daa-354796bedb74@intel.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <2b1b5ded-522f-1fcf-6daa-354796bedb74@intel.com>
User-Agent: Mutt/1.9.4 (2018-02-28)
Precedence: bulk

On Mon, Mar 20, 2023 at 09:44:04AM -0700, Dave Hansen wrote:
> On 3/14/23 16:16, Ricardo Neri wrote:
> > -static unsigned short num_cache_leaves;
> > +static DEFINE_PER_CPU(unsigned short, num_cache_leaves);
> > +
> > +static inline unsigned short get_num_cache_leaves(unsigned int cpu)
> > +{
> > +	return per_cpu(num_cache_leaves, cpu);
> > +}

Thank you very much for your feedback Dave!

> 
> I know it's in generic code, but we do already have this:
> 
> static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cacheinfo);
> 
> which has a num_leaves in it:
> 
> struct cpu_cacheinfo {
>         struct cacheinfo *info_list;
>         unsigned int num_levels;
>         unsigned int num_leaves;
>         bool cpu_map_populated;
> };
> 
> That's currently _populated_ from the arch code that you are modifying.
> Do we really need this data stored identically in two different per-cpu
> locations?

That is a good observation. As you state, the ci_cpu_cacheinfo is already
initialized in the arch code. I can certainly modify the patch to make use
of it instead adding a new per-CPU variable.

> 
> I'd also love to hear some more background on "Intel Meteor Lake" and
> _why_ it has an asymmetric cache topology.

Meteor Lake has cores in more than one die. The cache to which these cores
are connected is different in each die. This is reflected in CPUID leaf 4.

Thanks and BR,
Ricardo