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From:   Hal Feng <hal.feng@starfivetech.com>
To:     <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>
CC:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor@kernel.org>,
        "Palmer Dabbelt" <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        Hal Feng <hal.feng@starfivetech.com>,
        <linux-kernel@vger.kernel.org>
Subject: [PATCH v1] riscv: dts: starfive: jh7110: Correct the properties of S7 core
Date:   Fri, 24 Mar 2023 14:46:51 +0800
Message-ID: <20230324064651.84670-1-hal.feng@starfivetech.com>
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The S7 core has no L1 data cache and MMU, so delete some
related properties.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---

Hi, Conor,

This is a correction for the S7 entry.
This patch depends on patch [1].

[1] https://lore.kernel.org/all/20230320103750.60295-20-hal.feng@starfivetech.com/

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..4c5fdb905da8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -20,21 +20,12 @@ cpus {
 		S7_0: cpu@0 {
 			compatible = "sifive,s7", "riscv";
 			reg = <0>;
-			d-cache-block-size = <64>;
-			d-cache-sets = <64>;
-			d-cache-size = <8192>;
-			d-tlb-sets = <1>;
-			d-tlb-size = <40>;
 			device_type = "cpu";
 			i-cache-block-size = <64>;
 			i-cache-sets = <64>;
 			i-cache-size = <16384>;
-			i-tlb-sets = <1>;
-			i-tlb-size = <40>;
-			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imac_zba_zbb";
-			tlb-split;
 			status = "disabled";
 
 			cpu0_intc: interrupt-controller {
-- 
2.38.1