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charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Hello,=0A= =0A= I have seen ~3 ms delay in interrupt handling on ARM64.=0A= =0A= I have traced it down to raw_spin_lock() call in handle_irq_event() in=0A= kernel/irq/handle.c:=0A= =0A= irqreturn_t handle_irq_event(struct irq_desc *desc)=0A= {=0A= irqreturn_t ret;=0A= =0A= desc->istate &=3D ~IRQS_PENDING;=0A= irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);=0A= raw_spin_unlock(&desc->lock);=0A= =0A= ret =3D handle_irq_event_percpu(desc);=0A= =0A= --> raw_spin_lock(&desc->lock);=0A= irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);=0A= return ret;=0A= }=0A= =0A= It took ~3 ms for this raw_spin_lock() to lock.=0A= =0A= During this time irq_finalize_oneshot() from kernel/irq/manage.c locks and= =0A= unlocks the same raw spin lock more than 1000 times:=0A= =0A= static void irq_finalize_oneshot(struct irq_desc *desc,=0A= struct irqaction *action)=0A= {=0A= if (!(desc->istate & IRQS_ONESHOT) ||=0A= action->handler =3D=3D irq_forced_secondary_handler)=0A= return;=0A= again:=0A= chip_bus_lock(desc);=0A= --> raw_spin_lock_irq(&desc->lock);=0A= =0A= /*=0A= * Implausible though it may be we need to protect us against=0A= * the following scenario:=0A= *=0A= * The thread is faster done than the hard interrupt handler=0A= * on the other CPU. If we unmask the irq line then the=0A= * interrupt can come in again and masks the line, leaves due=0A= * to IRQS_INPROGRESS and the irq line is masked forever.=0A= *=0A= * This also serializes the state of shared oneshot handlers=0A= * versus "desc->threads_oneshot |=3D action->thread_mask;" in=0A= * irq_wake_thread(). See the comment there which explains the=0A= * serialization.=0A= */=0A= if (unlikely(irqd_irq_inprogress(&desc->irq_data))) {=0A= --> raw_spin_unlock_irq(&desc->lock);=0A= chip_bus_sync_unlock(desc);=0A= cpu_relax();=0A= goto again;=0A= }=0A= ...=0A= =0A= I have created a workaround for this problem by calling cpu_relax() 50=0A= times after 100 failed tries. See attached patch=0A= 3ms_tx_delay_workaround.patch.=0A= =0A= I have created custom kernel module with 2 threads, one similar to=0A= irq_finalize_oneshot(), second similar to handle_irq_event(). I have used= =0A= latest Linux 6.3-rc3 with no added patches and I confirmed that even there= =0A= qspinlocks are not fair on my ARM64 board.=0A= =0A= I copied qspinlocks code to the module twice and I have put traces only to= =0A= one thread, the one which takes several ms to lock and is originally=0A= called from handle_irq_event(). I have found out that the=0A= queued_fetch_set_pending_acquire() takes those 3 ms to finish. On ARM64=0A= queued_fetch_set_pending_acquire() is implemented as=0A= atomic_fetch_or_acquire().=0A= =0A= I have found out that my CPU doesn't know LSE atomic instructions and it=0A= looks like atomic operations could be quite slow there. Assembler code in= =0A= arch/arm64/include/asm/atomic_ll_sc.h has loop inside:=0A= =0A= #define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint) \= =0A= static __always_inline int \=0A= __ll_sc_atomic_fetch_##op##name(int i, atomic_t *v) \=0A= { \=0A= unsigned long tmp; \=0A= int val, result; \=0A= \=0A= asm volatile("// atomic_fetch_" #op #name "\n" \=0A= " prfm pstl1strm, %3\n" \=0A= "1: ld" #acq "xr %w0, %3\n" \=0A= " " #asm_op " %w1, %w0, %w4\n" \=0A= " st" #rel "xr %w2, %w1, %3\n" \=0A= --> " cbnz %w2, 1b\n" \=0A= " " #mb \=0A= : "=3D&r" (result), "=3D&r" (val), "=3D&r" (tmp), "+Q" (v->counter) \= =0A= : __stringify(constraint) "r" (i) \=0A= : cl); \=0A= \=0A= return result; \=0A= }=0A= =0A= Most importantly, these atomic operations seem to make one CPU dominate=0A= the cache line so that the other is unable to take the lock. And that is=0A= problematic in combination with the retry loop in irq_finalize_oneshot().= =0A= =0A= To confirm it I have created small userspace program, which just calls=0A= __ll_sc_atomic_fetch_or_acquire() from two threads. See attached=0A= unfair_arm64_asm_atomic_ll_sc_demonstration.tar.gz. Bellow you can see=0A= that it took 16 ms for one atomic operation.=0A= =0A= # ./contested=0A= load thread started=0A= evaluation thread started=0A= new max duration: 6420 ns=0A= new max duration: 9355 ns=0A= new max duration: 22240 ns=0A= new max duration: 23180 ns=0A= new max duration: 70465 ns=0A= new max duration: 77860 ns=0A= new max duration: 83100 ns=0A= new max duration: 105115 ns=0A= new max duration: 127695 ns=0A= new max duration: 128840 ns=0A= new max duration: 1265595 ns=0A= new max duration: 3713430 ns=0A= new max duration: 3750810 ns=0A= new max duration: 7996020 ns=0A= new max duration: 7998890 ns=0A= new max duration: 7999340 ns=0A= new max duration: 7999490 ns=0A= new max duration: 12000210 ns=0A= new max duration: 15999700 ns=0A= new max duration: 16000000 ns=0A= new max duration: 16000030 ns=0A= =0A= So I confirmed that atomic operations from=0A= arch/arm64/include/asm/atomic_ll_sc.h can be quite slow when they are=0A= contested from second CPU.=0A= =0A= Do you think that it is possible to create fair qspinlock implementation=0A= on top of atomic instructions supported by ARM64 version 8 (no LSE atomic= =0A= instructions) without compromising performance in the uncontested case?=0A= For example ARM64 could have custom queued_fetch_set_pending_acquire=0A= implementation same as x86 has in arch/x86/include/asm/qspinlock.h. Is the= =0A= retry loop in irq_finalize_oneshot() ok together with the current ARM64=0A= cpu_relax() implementation for processor with no LSE atomic instructions?= =0A= =0A= I reproduced the real life scenario of TX delay only in ICSSG network=0A= driver (not yet merged to mainline) [1], it was with kernel 5.10 with=0A= patches, CONFIG_PREEMPT_RT and custom ICSSG firmware on Texas Instruments= =0A= AM65x IDK [2] with ARM Cortex A53. This custom setup comes with high=0A= interrupt load.=0A= =0A= [1] https://lore.kernel.org/all/20220406094358.7895-1-p-mohan@ti.com/=0A= [2] https://www.ti.com/tool/TMDX654IDKEVM=0A= =0A= With best regards,=0A= Zdenek Bouska=0A= =0A= --=0A= Siemens, s.r.o=0A= Siemens Advanta Development= --_003_AS1PR10MB56750EFD7BEA779D033A68CBEB849AS1PR10MB5675EURP_ Content-Type: application/x-gzip; name="unfair_arm64_asm_atomic_ll_sc_demonstration.tar.gz" Content-Description: unfair_arm64_asm_atomic_ll_sc_demonstration.tar.gz Content-Disposition: attachment; filename="unfair_arm64_asm_atomic_ll_sc_demonstration.tar.gz"; size=3522; creation-date="Fri, 24 Mar 2023 08:34:29 GMT"; modification-date="Fri, 24 Mar 2023 08:40:53 GMT" Content-Transfer-Encoding: base64 H4sIAAAAAAAAA+1be3PbNhLPv9Kn2MqTVnQlWaQeTqwmM4rsOD4rts9yer1pehyKgiy2FMnyYcvJ 5Lvfgk/wJYmq60xbbhuZBLALLPYH7C5IOtpcUkxRMpf9rihZS1Gy9aUii6oqWrI4I0tds2xTshVd O3i2I7WRDg979C9/2GuzfwN6xne77X6n1zvsd5+1Bb7d7TyD3q4dFiHHsiUT4NmndrsrTF/+mtdu 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