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Date:   Fri, 24 Mar 2023 19:05:34 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Hal Feng <hal.feng@starfivetech.com>
Cc:     devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] riscv: dts: starfive: jh7110: Correct the properties
 of S7 core
Message-ID: <225945e3-2610-4fec-8ee5-5893d26641b4@spud>
References: <20230324064651.84670-1-hal.feng@starfivetech.com>
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On Fri, Mar 24, 2023 at 02:46:51PM +0800, Hal Feng wrote:
> The S7 core has no L1 data cache and MMU, so delete some
> related properties.
>=20
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>=20
> Hi, Conor,
>=20
> This is a correction for the S7 entry.

Again going off the latest version of the u74-mc core complex, this
looks to be correct, thanks.
I need to go read the Emil email from earier today, but I've
provisionally gone and put this on the riscv-jh7100_initial_dts branch
with a Fixes: tag.

Thanks,
Conor.

> This patch depends on patch [1].
>=20
> [1] https://lore.kernel.org/all/20230320103750.60295-20-hal.feng@starfive=
tech.com/
>=20
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ---------
>  1 file changed, 9 deletions(-)
>=20
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/d=
ts/starfive/jh7110.dtsi
> index d484ecdf93f7..4c5fdb905da8 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -20,21 +20,12 @@ cpus {
>  		S7_0: cpu@0 {
>  			compatible =3D "sifive,s7", "riscv";
>  			reg =3D <0>;
> -			d-cache-block-size =3D <64>;
> -			d-cache-sets =3D <64>;
> -			d-cache-size =3D <8192>;
> -			d-tlb-sets =3D <1>;
> -			d-tlb-size =3D <40>;
>  			device_type =3D "cpu";
>  			i-cache-block-size =3D <64>;
>  			i-cache-sets =3D <64>;
>  			i-cache-size =3D <16384>;
> -			i-tlb-sets =3D <1>;
> -			i-tlb-size =3D <40>;
> -			mmu-type =3D "riscv,sv39";
>  			next-level-cache =3D <&ccache>;
>  			riscv,isa =3D "rv64imac_zba_zbb";
> -			tlb-split;
>  			status =3D "disabled";
> =20
>  			cpu0_intc: interrupt-controller {
> --=20
> 2.38.1
>=20

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