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From:   "Bouska, Zdenek" <zdenek.bouska@siemens.com>
To:     Catalin Marinas <catalin.marinas@arm.com>
CC:     Thomas Gleixner <tglx@linutronix.de>,
        Will Deacon <will@kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Kiszka, Jan" <jan.kiszka@siemens.com>,
        "linux-rt-users@vger.kernel.org" <linux-rt-users@vger.kernel.org>,
        Nishanth Menon <nm@ti.com>, Puranjay Mohan <p-mohan@ti.com>
Subject: Re: Unfair qspinlocks on ARM64 without LSE atomics => 3ms delay in
 interrupt handling
Thread-Topic: Unfair qspinlocks on ARM64 without LSE atomics => 3ms delay in
 interrupt handling
Thread-Index: AQHZXitnsElEVi8SeUyEotrWHWfO2q8KKDUAgAP4mD0=
Date:   Mon, 27 Mar 2023 05:44:30 +0000
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>> So I confirmed that atomic operations from=0A=
>> arch/arm64/include/asm/atomic_ll_sc.h can be quite slow when they are=0A=
>> contested from second CPU.=0A=
>> =0A=
>> Do you think that it is possible to create fair qspinlock implementation=
=0A=
>> on top of atomic instructions supported by ARM64 version 8 (no LSE atomi=
c=0A=
>> instructions) without compromising performance in the uncontested case?=
=0A=
>> For example ARM64 could have custom queued_fetch_set_pending_acquire=0A=
>> implementation same as x86 has in arch/x86/include/asm/qspinlock.h. Is t=
he=0A=
>> retry loop in irq_finalize_oneshot() ok together with the current ARM64=
=0A=
>> cpu_relax() implementation for processor with no LSE atomic instructions=
?=0A=
>=0A=
>So is the queued_fetch_set_pending_acquire() where it gets stuck or the=0A=
>earlier atomic_try_cmpxchg_acquire() before entering on the slow path? I=
=0A=
>guess both can fail in a similar way.=0A=
=0A=
For me it was stuck on queued_fetch_set_pending_acquire().=0A=
=0A=
Zdenek Bouska=0A=
=0A=
--=0A=
Siemens, s.r.o=0A=
Siemens Advanta Development=