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Message-ID: <a17cd888-ef4d-ced0-adba-c6a6abdba51a@linaro.org>
Date:   Mon, 27 Mar 2023 11:29:56 +0100
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Subject: Re: [PATCH v2 1/2] mtd: rawnand: stm32_fmc2: do not support EDO mode
Content-Language: en-US
To:     Christophe Kerello <christophe.kerello@foss.st.com>,
        miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com
Cc:     linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com
References: <20230327094742.38856-1-christophe.kerello@foss.st.com>
 <20230327094742.38856-2-christophe.kerello@foss.st.com>
From:   Tudor Ambarus <tudor.ambarus@linaro.org>
In-Reply-To: <20230327094742.38856-2-christophe.kerello@foss.st.com>
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Hi,

On 3/27/23 10:47, Christophe Kerello wrote:
> FMC2 controller does not support EDO mode (timings mode 4 and 5).
> 

commit subject and message should be in imperative mood, so I would
change the commit subject to "mtd: rawnand: stm32_fmc2: Remove
unsupported EDO mode" and the message to something like "Remove the EDO
mode support from as the FMC2 controller does not support the feature."
Extra points if you describe what happened when you used timings mode 4
and 5 with the current version of the driver.

Miquel, could you add Cc to stable when applying?
Cc: stable@vger.kernel.org

> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
> Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver")

Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>

> ---
>  drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> index 5d627048c420..3abb63d00a0b 100644
> --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> @@ -1531,6 +1531,9 @@ static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr,
>  	if (IS_ERR(sdrt))
>  		return PTR_ERR(sdrt);
>  
> +	if (sdrt->tRC_min < 30000)
> +		return -EOPNOTSUPP;
> +
>  	if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
>  		return 0;
>