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Subject: Re: [PATCH V10 2/4] clk: qcom: Add Global Clock Controller driver for IPQ9574
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     quic_srichara@quicinc.com, quic_gokulsri@quicinc.com,
        quic_sjaganat@quicinc.com, quic_kathirav@quicinc.com,
        quic_arajkuma@quicinc.com, quic_anusha@quicinc.com,
        quic_poovendh@quicinc.com
To:     Devi Priya <quic_devipriy@quicinc.com>, agross@kernel.org,
        andersson@kernel.org, arnd@arndb.de, broonie@kernel.org,
        catalin.marinas@arm.com, devicetree@vger.kernel.org,
        dmitry.baryshkov@linaro.org, konrad.dybcio@linaro.org,
        krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org,
        linux-arm-kernel@lists.infradead.org,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
        marcel.ziswiler@toradex.com, mturquette@baylibre.com,
        nfraprado@collabora.com, p.zabel@pengutronix.de,
        robh+dt@kernel.org, shawnguo@kernel.org, will@kernel.org
Date:   Mon, 27 Mar 2023 09:48:47 -0700
User-Agent: alot/0.10
Precedence: bulk

Quoting Devi Priya (2023-03-27 06:27:16)
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq957=
4.c
> new file mode 100644
> index 000000000000..b2a2d618a5ec
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -0,0 +1,4248 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2023 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>

What is this include for?

> +#include <linux/regmap.h>

Need to include clk-provider.h

> +
> +#include <linux/reset-controller.h>

Put a newline here.

> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> +#include "reset.h"
> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> +       DT_XO,
> +       DT_SLEEP_CLK,
> +       DT_BIAS_PLL_UBI_NC_CLK,
> +       DT_PCIE30_PHY0_PIPE_CLK,
> +       DT_PCIE30_PHY1_PIPE_CLK,
> +       DT_PCIE30_PHY2_PIPE_CLK,
> +       DT_PCIE30_PHY3_PIPE_CLK,
> +       DT_USB3PHY_0_CC_PIPE_CLK,
> +};
> +
> +enum {
> +       P_XO,
> +       P_PCIE30_PHY0_PIPE,
> +       P_PCIE30_PHY1_PIPE,
> +       P_PCIE30_PHY2_PIPE,
> +       P_PCIE30_PHY3_PIPE,
> +       P_USB3PHY_0_PIPE,
> +       P_GPLL0,
> +       P_GPLL0_DIV2,
> +       P_GPLL0_OUT_AUX,
> +       P_GPLL2,
> +       P_GPLL4,
> +       P_PI_SLEEP,
> +       P_BIAS_PLL_UBI_NC_CLK,
> +};
> +
> +static const struct parent_map gcc_xo_map[] =3D {
> +       { P_XO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_data[] =3D {
> +       { .index =3D DT_XO },
> +};
> +
> +static const struct clk_parent_data gcc_sleep_clk_data[] =3D {
> +       { .index =3D DT_SLEEP_CLK },
> +};
> +
> +static struct clk_alpha_pll gpll0_main =3D {
> +       .offset =3D 0x20000,
> +       .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +       .clkr =3D {
> +               .enable_reg =3D 0x0b000,
> +               .enable_mask =3D BIT(0),
> +               .hw.init =3D &(struct clk_init_data) {

All these clk_init_data structs should be const.

> +                       .name =3D "gpll0_main",
> +                       .parent_data =3D gcc_xo_data,
> +                       .num_parents =3D ARRAY_SIZE(gcc_xo_data),
> +                       .ops =3D &clk_alpha_pll_ops,
> +               },
> +       },
> +};